MPC5125 datasheet(75/92 Pages) FREESCALE

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Electrical and Thermal Characteristics

MPC5125 Microcontroller Data Sheet, Rev. 3

Freescale Semiconductor

Figure 40. Timing Diagram — AC97 Mode

4.3.15.3

SPI Mode

Table 42. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0) 1

NOTES:

1 Output timing is specified at a nominal 50 pF load.

Sym

Description

Min

Max

Units

SpecID

SCK cycle time, programable in the PSC CCS register

30.0

—

A20.26

SCK pulse width, 50% SCK duty cycle

15.0

—

A20.27

Slave select clock delay, programable in the PSC CCS register

30.0

—

A20.28

Output data valid after slave select (SS)—

8.9

A20.29

Output data valid after SCK

—

8.9

A20.30

Input data setup time

6.0

—

A20.31

Input data hold time

1.0

—

A20.32

Slave disable lag time

—

TSCK

A20.33

Sequential transfer delay, programable in the PSC CTUR / CTLR register

15.0

—

A20.34

Clock falling time

—

7.9

A20.35

Clock rising time

—

7.9

A20.36

BitClk

(CLKPOL=0)

FrameSync

(SyncPol= 1)

Sdata_out

Output

Input

Output

Sdata_in

Input

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