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MPC5125 Datasheet(PDF) 70 Page - Freescale Semiconductor, Inc |
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MPC5125 Datasheet(HTML) 70 Page - Freescale Semiconductor, Inc |
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70 / 92 page  MPC5125 Microcontroller Data Sheet, Rev. 3 Electrical and Thermal Characteristics Freescale Semiconductor 70 The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register; The PW_H, BP_H, and FP_H parameters are programmed via the HSYN_PARA register; and the PW_V, BP_V, and FP_V parameters are programmed via the VSYN_PARA register. See appropriate section in the reference manual for detailed descriptions of these parameters. Figure 36 depicts the synchronous display interface timing for access level, and Table 36 lists the timing parameters. Figure 36. LCD Interface Timing Diagram — Access Level tFPH HSYNC Front Porch Width FP_H × t PCP ns A15.4 tSW Screen Width DELTA_X × t PCP ns A15.5 tHSP HSYNC (Line) Period (PW_H + BP_H + DELTA_X + FP_H) × t PCP ns A15.6 tPWV VSYNC Pulse Width PW_V × t HSP ns A15.7 tBPV VSYNC Back Porch Width BP_V × t HSP ns A15.8 tFPV VSYNC Front Porch Width FP_V × t HSP ns A15.9 tSH Screen Height DELTA_Y × t HSP ns A15.10 tVSP VSYNC (Frame) Period (PW_V + BP_V + DELTA_Y + FP_H) × t HSP ns A15.11 NOTES: 1 Display interface pixel clock period immediate value (in nanoseconds). Table 36. LCD Interface Timing Parameters — Access Level Parameter Description Min Typ Max Unit SpecID tCKH LCD interface pixel clock high time tPCP × 0.4 tPCP × 0.5 tPCP × 0.6 ns A15.12 tCKL LCD interface pixel clock low time tPCP × 0.4 tPCP × 0.5 tPCP × 0.6 ns A15.13 tDSU LCD interface data setup time 5.0 — — ns A15.14 tDHD LCD interface data hold time 6.0 — — ns A15.15 tCSU LCD interface control signal setup time 5.0 — — ns A15.16 tCHD LCD interface control signal hold time 6.0 — — ns A15.17 Table 35. LCD Interface Timing Parameters — Pixel Level Sym Description Value Unit SpecID tCKH tCKL tDHD tDSU tCSU DIU_HSYNC DIU_VSYNC DIU_DE DIU_CLK DIU_LD[23:0] tCHD |
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