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MRF24J40-I/T Datasheet(PDF) 35 Page - Microchip Technology |
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MRF24J40-I/T Datasheet(HTML) 35 Page - Microchip Technology |
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35 / 156 page  REGISTER 2-23: PACON2: POWER AMPLIFIER CONTROL 2 REGISTER (ADDRESS: 0x18) R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 FIFOEN r TXONTS3(1) TXONTS2(1) TXONTS1(1) TXONTS0(1) TXONT8(1) TXONT7(1) bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 FIFOEN: FIFO Enable bit 1 = Enabled (default). Always maintain this bit as a ‘1’. bit 6 Reserved: Maintain as ‘0’ bit 5-2 TXONTS<3:0>: Transmitter Enable On Time Symbol bits(1) Transmitter on time before beginning of packet. Units: symbol period (16 μs). Minimum value: 0x1. Default value: 0x2 (2 * 16 μs = 32 μs). Recommended value: 0x6 (6 * 16 μs = 96 μs). bit 1-0 TXONT<8:7>: Transmitter Enable On Time Tick bits(1) Transmitter on time before beginning of packet. TXONT is a 9-bit value. TXONT<6:0> bits are located in SYMTICKH<7:1>. Units: tick (50 ns). Default value = 0x028 (40 * 50 ns = 2 μs). Note 1: Refer to Figure 4-4 for timing diagram. © 2010 Microchip Technology Inc. Preliminary DS39776C-page 35 MRF24J40 |
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