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MRF24J40-I/T Datasheet(PDF) 48 Page - Microchip Technology |
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MRF24J40-I/T Datasheet(HTML) 48 Page - Microchip Technology |
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48 / 156 page  REGISTER 2-40: SOFTRST: SOFTWARE RESET REGISTER (ADDRESS: 0x2A) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 W-0 W-0 W-0 r r r r r RSTPWR RSTBB RSTMAC bit 7 bit 0 Legend: r = reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Reserved: Maintain as ‘0’ bit 2 RSTPWR: Power Management Reset bit 1 = Reset power management circuitry (bit is automatically cleared to ‘0’ by hardware) bit 1 RSTBB: Baseband Reset bit 1 = Reset baseband circuitry (bit is automatically cleared to ‘0’ by hardware) bit 0 RSTMAC: MAC Reset bit 1 = Reset MAC circuitry (bit is automatically cleared to ‘0’ by hardware) MRF24J40 DS39776C-page 48 Preliminary © 2010 Microchip Technology Inc. |
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