P89V51RB2BBC datasheet(69/80 Pages) NXP

69 / 80 page

P89V51RB2_RC2_RD2_5

Product data sheet

Rev. 05 — 12 November 2009

69 of 80

NXP Semiconductors

P89V51RB2/RC2/RD2

8-bit microcontrollers with 80C51 core

Fig 35. Shift register mode timing waveforms

002aaa552

ALE

instruction

valid

TXLXL

set TI

set RI

tXHQX

tQVXH

tXHDV

tXHDX

clock

output data

write to SBUF

input data

clear RI

Table 66.

SPI interface timing

Symbol

Parameter

Conditions

Variable clock

fosc =18MHz

Unit

Min

Max

Min

Max

fSPI

SPI operating frequency

Tcy(clk) / 4

MHz

TSPICYC

SPI cycle time

see Figure 36, 37, 38, 39

4Tcy(clk)

222

tSPILEAD

SPI enable lead time

see Figure 38, 39

250

tSPILAG

SPI enable lag time

see Figure 38, 39

250

tSPICLKH

SPICLK HIGH time

see Figure 36, 37, 38, 39

2Tcy(clk)

111

tSPICLKL

SPICLK LOW time

see Figure 36, 37, 38, 39

2Tcy(clk)

111

tSPIDSU

SPI data set-up time

master or slave; see

Figure 36, 37, 38, 39

100

tSPIDH

SPI data hold time

master or slave; see

Figure 36, 37, 38, 39

100

tSPIA

SPI access time

see Figure 38, 39

tSPIDIS

SPI disable time

see Figure 38, 39

160

tSPIDV

SPI enable to output

data valid time

see Figure 36, 37, 38, 39

111

tSPIOH

SPI output data hold

time

see Figure 36, 37, 38, 39

tSPIR

SPI rise time

see Figure 36, 37, 38, 39

SPI outputs (SPICLK,

MOSI, MISO)

100

SPI inputs (SPICLK,

MOSI, MISO, SS)

2000

tSPIF

SPI fall time

see Figure 36, 37, 38, 39

SPI outputs (SPICLK,

MOSI, MISO)

100

SPI inputs (SPICLK,

MOSI, MISO, SS)

2000

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