P89V51RB2BBC datasheet(9/80 Pages) NXP

9 / 80 page

P89V51RB2_RC2_RD2_5

Product data sheet

Rev. 05 — 12 November 2009

9 of 80

NXP Semiconductors

P89V51RB2/RC2/RD2

8-bit microcontrollers with 80C51 core

[1]

ALE loading issue: When ALE pin experiences higher loading (>30 pF) during the reset, the microcontroller may accidentally enter into

modes other than normal working mode. The solution is to add a pull-up resistor of 3 k

Ω to 50 kΩ to V

DD, e.g., for ALE pin.

[2]

For 6-clock mode, ALE is emitted at 1

⁄

3 of crystal frequency.

RST

Reset: While the oscillator is running, a HIGH logic state

on this pin for two machine cycles will reset the device. If

the PSEN pin is driven by a HIGH-to-LOW input transition

while the RST input pin is held HIGH, the device will enter

the external host mode, otherwise the device will enter the

normal operation mode.

External Access Enable: EA must be connected to VSS in

order to enable the device to fetch code from the external

program memory. EA must be strapped to VDD for internal

program execution. The EA pin can tolerate a high voltage

of 12 V.

ALE/PROG

I/O

Address Latch Enable: ALE is the output signal for

latching the low byte of the address during an access to

external memory. This pin is also the programming pulse

input (PROG) for ﬂash programming. Normally the ALE[1]

is emitted at a constant rate of 1

⁄6 the crystal frequency[2]

and can be used for external timing and clocking. One ALE

pulse is skipped during each access to external data

memory. However, if AO is set to ‘1’, ALE is disabled.

n.c.

6, 17, 28,

1, 12, 23,

I/O

not connected

XTAL1

Crystal 1: Input to the inverting oscillator ampliﬁer and

input to the internal clock generator circuits.

XTAL2

Crystal 2: Output from the inverting oscillator ampliﬁer.

VDD

Power supply

VSS

Ground

Table 3.

P89V51RB2/RC2/RD2 pin description …continued

Symbol

Type

Description

DIP40

TQFP44

PLCC44

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