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TMS320F28023DAS Datasheet(PDF) 86 Page - Texas Instruments |
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TMS320F28023DAS Datasheet(HTML) 86 Page - Texas Instruments |
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86 / 130 page ![]() Transmission Line 4.0 pF 1.85 pF Z0 = 50 W (A) Tester Pin Electronics Data Sheet Timing Reference Point Output Under Test 42 W 3.5 nH Device Pin (B) TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022 TMS320F28021, TMS320F28020, TMS320F280200 SPRS523F – NOVEMBER 2008 – REVISED DECEMBER 2010 www.ti.com 6.7 Timing Parameter Symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: Lowercase subscripts and their Letters and symbols and their meanings: meanings: a access time H High c cycle time (period) L Low d delay time V Valid Unknown, changing, or don't care f fall time X level h hold time Z High impedance r rise time su setup time t transition time v valid time w pulse duration (width) 6.7.1 General Notes on Timing Parameters All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this document. 6.7.2 Test Load Circuit This test load circuit is used to measure all switching characteristics provided in this document. A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timing. Figure 6-4. 3.3-V Test Load Circuit 86 Electrical Specifications Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200 |
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