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SPC5668EF1AVMG Datasheet(PDF) 47 Page - Freescale Semiconductor, Inc |
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SPC5668EF1AVMG Datasheet(HTML) 47 Page - Freescale Semiconductor, Inc |
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47 / 66 page ![]() Electrical Characteristics MPC5668x Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 47 4.14.4 Nexus Debug Interface Figure 13. Nexus Output Timing Table 27. Nexus Debug Port Timing1 1 JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDDE =3.0–5.5 V, TA =TL to TH, and CL =30pF with SRC = 0b11. Spec Characteristic Symbol Min Max Unit 1 MCKO Cycle Time tMCYC 15.6 — ns 2 MCKO Duty Cycle tMDC 40 60 % 3 MCKO Low to MDO, MSEO, EVTO Data Valid2 2 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. tMDOV –0.1 0.25 tMCYC 4 EVTI Pulse Width tEVTIPW 4.0 — tTCYC 5 EVTO Pulse Width tEVTOPW 1tMCYC 6 TCK Cycle Time3 3 The system clock frequency needs to be three times faster than the TCK frequency. tTCYC 40 — ns 7 TCK Duty Cycle tTDC 40 60 % 8 TDI, TMS Data Setup Time tNTDIS, tNTMSS 8— ns 9 TDI, TMS Data Hold Time tNTDIH, tNTMSH 5— ns 10 TCK Low to TDO Data Valid tJOV 025 ns 1 2 MCKO MDO MSEO EVTO Output Data Valid 3 EVTI 4 5 |
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