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SPC5668EF1AVMG Datasheet(PDF) 59 Page - Freescale Semiconductor, Inc |
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SPC5668EF1AVMG Datasheet(HTML) 59 Page - Freescale Semiconductor, Inc |
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59 / 66 page ![]() Electrical Characteristics MPC5668x Microcontroller Data Sheet, Rev. 6 Freescale Semiconductor 59 4.14.8.3 MII Async Inputs Signal Timing (CRS and COL) Figure 28. MII Async Inputs Timing Diagram 4.14.8.4 MII Serial Management Channel Timing (MDIO and MDC) The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. Table 35. MII Async Inputs Signal Timing1 1 Output pads configured with SRC = 0b11. Spec Characteristic Min Max Unit M9 CRS, COL minimum pulse width 1.5 — TX_CLK period Table 36. MII Serial Management Channel Timing1 1 Output pads configured with SRC = 0b11. Spec Characteristic Min Max Unit M10 MDC falling edge to MDIO output invalid (minimum propagation delay) 0 — ns M11 MDC falling edge to MDIO output valid (max prop delay) — 25 ns M12 MDIO (input) to MDC rising edge setup 10 — ns M13 MDIO (input) to MDC rising edge hold 0 — ns M14 MDC pulse width high 40% 60% MDC period M15 MDC pulse width low 40% 60% MDC period CRS, COL M9 |
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