R5F107ACMSP datasheet(39/107 Pages) RENESAS

39 / 107 page

RL78/G1C

ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85

°C)

Page 39 of 135

R01DS0348EJ0100

Rev.1.00

Aug 08, 2013

(3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)

(TA =

−40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to

SCKp

↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from

SCKp

↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output

becomes “from SCKp

↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

4. C is the load capacitance of the SCKp and SOp output lines.

Caution

Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and

SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).

Remarks 1.

p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),

g: PIM and POM numbers (g = 0, 3, 5, 7)

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00, 01))

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

2.7 V

≤ VDD ≤ 5.5 V

167

SCKp cycle time

tKCY1

≥ 4/fCLK

2.4 V

≤ VDD ≤ 5.5 V

250

4.0 V

≤ VDD ≤ 5.5 V

tKCY1/2

− 12

2.7 V

≤ VDD ≤ 5.5 V

tKCY1/2

− 18

SCKp high-/low-level width

tKH1,

tKL1

2.4 V

≤ VDD ≤ 5.5 V

tKCY1/2

− 38

4.0 V

≤ VDD ≤ 5.5 V

2.7 V

≤ VDD ≤ 5.5 V

SIp setup time (to SCKp

↑) Note 1

tSIK1

2.4 V

≤ VDD ≤ 5.5 V

SIp hold time (from SCKp

↑) Note 2

tKSI1

Delay time from SCKp

↓ to

SOp output

Note 3

tKSO1

C = 30 pF

Note 4

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