PCMB065T-2R2MS datasheet(16/47 Pages) IRF

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Dual output, 4A/Phase, Highly Integrated SupIRBuck

Single-Input Voltage, Synchronous Buck Regulator

IR3891

www.irf.com

May 08, 2013

THEORY OF OPERATION

DESCRIPTION

The IR3891 uses a PWM voltage mode control

scheme with external compensation to provide good

noise immunity and maximum flexibility in selecting

inductor values and capacitor types.

The switching frequency is programmable from

300KHz to 1.5MHz and provides the capability of

optimizing the design in terms of size and

performance.

IR3891 provides precisely regulated output voltage

programmed via two external resistors from 0.5V to

0.86*PVin.

The IR3891 operates with an internal low drop out

regulator (LDO) which is connected to the VCC pin.

This allows operation with a single supply. When

using the internal LDO supply, the Vin pin should be

connected the PVin pin. If an external bias is used, it

should be connected to the VCC pin and the Vin pin

should be shorted to the VCC pin.

The device utilizes the on-resistance of the low side

MOSFET (sync FET) as a current sense element.

This method enhances the converter’s efficiency and

reduces cost by eliminating the need for an external

current sense resistor.

IR3891 includes two low Rds(on) MOSFETs using

IR’s HEXFET technology.

These are specifically

designed for high efficiency applications.

UNDER-VOLTAGE LOCKOUT AND POR

The under-voltage lockout circuits monitor the voltage

on the VCC pin and the EN1/2 pins. They ensure that

the MOSFET driver outputs remain in the off state

whenever either of these signals drops below the set

thresholds. Normal operation resumes once VCC and

EN rise above their thresholds.

The POR (Power On Ready) signal is high when all

these signals reach the valid logic level (see system

block diagram).

ENABLE

The EN pin offers another level of flexibility for startup.

Each channel of the IR3891 is controlled by a

separate EN pin. When the voltage at an EN pin

voltage

exceeds

its

precise

threshold

(EN_UVLO_START), the respective channel turns on.

The precise threshold allows the user to implement an

Under-Voltage Lockout (UVLO) function. By deriving

the EN pin voltage from the bus voltage (PVin)

through a suitable resistor divider, the user can set a

PVin threshold voltage. The resistor divider scales the

PVin voltage for the EN pin.

Only after the bus

voltage reaches or exceeds this level will the voltage

at the Enable pin exceeds its threshold and enable the

respective IR3891 channel. By connecting IR3891 in

this configuration, the user can enable the part by

applying PVin and ensures the IR3891 does not turn

on until the bus voltage reaches the desired level

(Figure 4). Therefore, in addition to being a logic input

pin that enables channels on IR3891, the EN pin also

offers UVLO functionality. UVLO functionality is

particularly

desirable

for

high

output

voltage

applications, where it is beneficial to disable the

IR3891 until PVin exceeds the desired output voltage

level.

Figure 4: Normal Startup: IR3891 Channel starts when

PVin reaches 10.2V by connecting EN to PVin using a

resistor divider.

PCMB065T-2R2MS Datasheet(PDF) 16 Page - International Rectifier

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