PCMB065T-2R2MS datasheet(20/47 Pages) IRF

20 / 47 page

Dual output, 4A/Phase, Highly Integrated SupIRBuck

Single-Input Voltage, Synchronous Buck Regulator

IR3891

www.irf.com

May 08, 2013

Figure 12: Timing diagram for Feed Forward (F.F.)

Function

LOW DROPOUT REGULATOR (LDO)

IR3891 has an integrated low dropout (LDO) regulator

which can provide gate drive voltage for both drivers.

When using an internally biased configuration, the

LDO draws from the Vin pin and provides a 5.3V

(typ.), as shown in Figure 13. Vin and PVin can be

connected together as shown in the internally biased

single rail configuration, Figure 14.

An external bias configuration can provide gate drive

voltage for the drivers instead of the internal LDO. To

use an external bias, connected to Vin and VCC to the

external bias, as shown in Figure 15. PVin can also

be connected or a different rail can be used.

When using multiple rail configurations, calculate the

compensation Vramp associated with Vin. Vramp is

derived from Vin which can be different from PVin,

refer to Feed-Forward section.

Figure 13: Internally Biased Configuration

Figure 14: Internally Biased Single Rail Configuration

Figure 15: Externally Biased Configuration

OUTPUT VOLTAGE SEQUENCING

IR3891 can accommodate user sequencing options

using Seq, EN1/2, and PGood1/2 pins. In the block

diagram presented on page 3, the error-amplifier (E/A)

has been depicted with three positive inputs. Ideally,

the input with the lowest voltage is used for regulating

the output voltage and the other two inputs are

ignored. In practice the voltages of the other two

inputs should be at least 200mV greater than the

referenced voltage input so that their effects can

completely be ignored.

In normal operating condition, the IR3891 channels

initially follow their internal soft-starts (Intl_SS) and

then references VREF.

After Enable goes high,

Intl_SS begins to ramp up from 0V.

The FB pin

follows the Intl_SS until it approaches VREF where

the E/A starts to reference the VREF instead of the

Intl_SS (refer to Figure 16).

VREF and Seq are not

referenced initially because they are higher than

Intl_SS. VREF is 0.5V, typical. Seq is internally pulled

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