PCMB065T-2R2MS datasheet(22/47 Pages) IRF

22 / 47 page

Dual output, 4A/Phase, Highly Integrated SupIRBuck

Single-Input Voltage, Synchronous Buck Regulator

IR3891

www.irf.com

May 08, 2013

Vcc

Vo1 (master)

Vo2 (slave)

(a)

Vo1 (master)

Vo2 (slave)

(b)

Intl_SS2

EN1

EN2

Figure 19: Typical waveforms for sequencing mode of

operation: (a) simultaneous, (b) ratiometric

OVER-VOLTAGE PROTECTION (OVP)

Over-Voltage protection (OVP) disables the channel

when the output voltage exceeds the over-voltage

threshold. IR3891 achieves OVP by comparing Vsns

pin to the internal over-voltage threshold set at

OVP(threshold), 1.2*VREF typical. Vsns voltage is

determined by an external voltage divider resistor

network connected to the output in typical application.

When Vsns exceeds the over-voltage threshold, an

over-voltage is detected and OV signal asserts after

OVP(delay). The high side drive signal HDrv is turned

off immediately and PGood flags low. The low side

drive signal is kept on until the Vsns voltage drops

below the lower threshold. After that, HDrv is latched

off until a reset is performed by cycling either VCC or

the respective EN.

Vsns

HDrv

LDrv

PGood

OVP(Threshold)

OVP(Hys)

2uS *

*typical filter delay

Figure 20: Timing diagram for OVP

OPEN FEEDBACK-LOOP PROTECTION

Open Feedback Loop protection (OFLP) is devised to

shutdown the channel in case the feedback is broken.

OFLP is activated when the Vsns is above the

VPG(upper) threshold, 0.85*VREF typical,

and

remains active while Vsns is above the VPG(lower)

threshold, 0.80*VREF.

When FB drop below

OFLP(threshold)

threshold,

0.70*VREF,

OFLP

disables switching and pulls down on PGood. The

part

remains

disabled

until

rises

above

OFLP(threshold) plus OFLP(Hys), 0.75*VREF. This

function does not latch the part off nor does it require

an EN or a VCC toggle to re-enable the part.

Figure 21: Timing Diagram for Open Feedback Line

Protection (OFLP)

POWER GOOD OUTPUT

PGood is an open drain pin that monitors the UV,

FAULT and the POR signals. PGood signal asserts

approximately

1.3mS,

after

Vsns

rises

above

VGP(Upper) threshold, 0.85*VREF typical, while

FAULT is low and POR is high. It remains asserted

while FAULT is low and POR is high and Vsns stays

above VGP(Lower) threshold, 0.80*VREF typical.

When Vsns falls below VGP(Lower) threshold there is

a typical 2µS delay before PGood goes low. The two

PGood signals are independent of each other and are

set according to their respective channel.

SWITCH NODE PHASE SHIFT

The two converters on the IR3891 run interleaving

phases by 180° to reduce input filter requirements.

The two converters are synchronized to the user

programmable oscillator. Channel 1 runs in phase with

the oscillator while channel 2 runs out of phase.

Staggering the switching cycles reduces the time the

converters

draw

current

from

the

supply

simultaneously. The pulses of current drawn from the

input induce voltage ripples across the input capacitor.

The voltage ripple shapes are dependent on the

different loading and output voltages of the two

converters. By switching the converters at different

times, the magnitude of voltage ripples reduces and

input filter requirements become less stringent.

PCMB065T-2R2MS Datasheet(PDF) 22 Page - International Rectifier

PCMB065T-2R2MS Datasheet(HTML) 22 Page - International Rectifier

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