PCMB065T-2R2MS datasheet(18/47 Pages) IRF

18 / 47 page

Dual output, 4A/Phase, Highly Integrated SupIRBuck

Single-Input Voltage, Synchronous Buck Regulator

IR3891

www.irf.com

May 08, 2013

Figure 9: Theoretical operation waveforms during soft-

start (non-sequencing)

OPERATING FREQUENCY

The switching frequency can be programmed between

300KHz-1.5MHz by connecting an external resistor

from Rt/Sync pin to GND.

Table 1 tabulates the

oscillator frequency versus Rt.

Table 1: Switching Frequency (Fs) vs. External

Resistor (Rt)

Rt (KΩ)

Freq

(KHz)

80.6

300

60.4

400

48.7

500

39.2

600

700

29.4

800

26.1

900

23.2

1000

1100

19.1

1200

17.6

1300

16.2

1400

1500

EXTERNAL SYNCHRONIZATION

IR3891 incorporates an internal phase lock loop (PLL)

circuit which enables synchronization of the internal

oscillator to an external clock.

This function is

important to avoid sub-harmonic oscillations due to

beat frequency for embedded systems when multiple

point-of-load (POL) regulators are used. A multiple-

function pin, Rt/Sync, is used to connect the external

clock.

If the external clock is present before the

converter turns on, Rt/Sync pin can be connected to

the external clock solely and no resistor is required. If

the external clock is applied after the converter turns

on, or the converter switching frequency needs to

toggle between the external clock frequency and the

internal free-running frequency, an external resistor

from Rt/Sync pin to GND is required to set the free

running frequency.

When an external clock is applied to Rt/Sync pin after

the converter runs in steady state with its free-running

frequency, a transition from the free-running frequency

to the external clock frequency will happen.

The

switching frequency gradually synchronizes to the

external clock frequency regardless of which one is

faster. On the contrary, when the external clock signal

is removed from Rt/Sync pin, the switching frequency

gradually returns to the free-running frequency. In

order to minimize the impact from these transitions to

output voltage, a diode is recommended to add

between the external clock and Rt/Sync pin. Figure 10

shows the timing diagram of these transitions.

SYNC

...

Gradually change

Fs1

Fs2

Fs1

Free Running

Frequency

Synchronize to the

external clock

Return to free-

running freq

Gradually change

Figure 10: Timing diagram for synchronization to an

external clock (Fs1>Fs2 or Fs1<Fs2)

An internal compensation circuit is used to change the

PWM ramp slope according to the clock frequency

applied on Rt/Sync pin. Thus, the effective amplitude

of the PWM ramp (Vramp), which is used in

compensation loop calculation, has minor impact from

the variation of the external synchronization signal.

Vin variation also affects the ramp amplitude, which is

discussed separately in Feed-Forward section.

SHUTDOWN

IR3891 shutdown occurs when VCC drops below its

threshold or a fault occurs. When VCC falls below

VCC_UVLO_STOP, the part detects an UVLO event

and the part turns off. Over-Voltage Protection, Over-

Current Protection and Thermal Shutdown also cause

the IR3891 shutdown. Faults are discussed in more

detail below.

PCMB065T-2R2MS Datasheet(PDF) 18 Page - International Rectifier

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