PCMB065T-2R2MS datasheet(24/47 Pages) IRF

24 / 47 page

Dual output, 4A/Phase, Highly Integrated SupIRBuck

Single-Input Voltage, Synchronous Buck Regulator

IR3891

www.irf.com

May 08, 2013

DESIGN EXAMPLE

The following example is a typical application for

IR3891. The application circuit is shown in

Vin = PVin = 12V (21V Max)

Fs = 600kHz

Channel 1:

Vo = 1.8V

Io = 4A

Ripple Voltage = ± 1% * Vo

∆Vo = ± 5% * Vo (for 50% load transient)

Channel

Vo = 1.2V

Io = 4A

Ripple Voltage = ± 1% * Vo

∆Vo = ± 5% * Vo (for 50% load transient)

Enabling the IR3891

As explained earlier, the precise threshold of the

Enable lends itself well to implementation of a UVLO

for the Bus Voltage as shown in Figure 23.

Figure 23: Using Enable pin for UVLO implementation

For a typical Enable threshold of VEN = 1.2 V

(min)







(8)





(min)

(9)

For PVin (min)=9.2V, R1=49.9K and R2=7.5K ohm is a

good choice.

Programming the frequency

For Fs = 600 kHz, select Rt = 39.2 KΩ, using Table 1.

Output Voltage Programming

Output voltage is programmed by reference voltage

and external voltage divider. The FB pin is the

inverting input of the error amplifier, which is internally

referenced to VREF. The divider ratio is set to equal

VREF at the FB pin when the output is at its desired

value. When an external resistor divider is connected

to the output as shown in Figure 24, the output

voltage is defined by using the following equation:



















ref

(10)



















ref

(11)

For the calculated values of R5 and R6, see feedback

compensation section.

Figure 24: Typical application of the IR3891

for programming the output voltage

Bootstrap Capacitor Selection

To drive the Control FET, it is necessary to supply a

gate voltage at least 4V greater than the voltage at the

SW pin, which is connected to the source of the

Control FET. This is achieved by using a bootstrap

configuration, which comprises the internal bootstrap

diode and an external bootstrap capacitor (C1). The

operation of the circuit is as follows: When the sync

FET is turned on, the capacitor node connected to SW

is pulled down to ground. The capacitor charges

towards Vcc through the internal bootstrap diode

(Figure 25), which has a forward voltage drop VD. The

voltage Vc across the bootstrap capacitor C1 is

approximately given as:





(12)

PCMB065T-2R2MS Datasheet(PDF) 24 Page - International Rectifier

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