PIC18F1220ESLASHSOSQTP datasheet(142/308 Pages) MICROCHIP

142 / 308 page

PIC18F1220/1320

DS39605F-page 140

FIGURE 16-1:

AUTOMATIC BAUD RATE CALCULATION

16.3

EUSART Asynchronous Mode

The Asynchronous mode of operation is selected by

clearing the SYNC bit (TXSTA<4>). In this mode, the

EUSART uses standard Non-Return-to-Zero (NRZ) for-

mat (one Start bit, eight or nine data bits and one Stop

bit). The most common data format is 8 bits. An on-chip

dedicated 8-bit/16-bit Baud Rate Generator can be

used to derive standard baud rate frequencies from the

oscillator.

The EUSART transmits and receives the LSb first. The

EUSART’s transmitter and receiver are functionally

independent, but use the same data format and baud

rate. The Baud Rate Generator produces a clock, either

x16 or x64 of the bit shift rate, depending on the BRGH

and BRG16 bits (TXSTA<2> and BAUDCTL<3>). Parity

is not supported by the hardware, but can be

implemented in software and stored as the 9th data bit.

Asynchronous mode is available in all low-power

modes; it is available in Sleep mode only when auto-

wake-up on Sync Break is enabled. When in PRI_IDLE

mode, no changes to the Baud Rate Generator values

are required; however, other low-power mode clocks

may operate at another frequency than the primary

clock. Therefore, the Baud Rate Generator values may

need to be adjusted.

When operating in Asynchronous mode, the EUSART

module consists of the following important elements:

• Baud Rate Generator

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

• Auto-Wake-up on Sync Break Character

• 12-bit Break Character Transmit

• Auto-Baud Rate Detection

16.3.1

EUSART ASYNCHRONOUS

TRANSMITTER

The EUSART transmitter block diagram is shown in

Figure 16-2. The heart of the transmitter is the Transmit

(Serial) Shift Register (TSR). The shift register obtains

its data from the Read/Write Transmit Buffer register,

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the Stop

bit has been transmitted from the previous load. As

soon as the Stop bit is transmitted, the TSR is loaded

with new data from the TXREG register (if available).

Once the TXREG register transfers the data to the TSR

empty and flag bit, TXIF (PIR1<4>), is set. This interrupt

can be enabled/disabled by setting/clearing enable bit,

TXIE (PIE1<4>). Flag bit, TXIF, will be set, regardless of

the state of enable bit, TXIE, and cannot be cleared in

software. Flag bit, TXIF, is not cleared immediately upon

loading the Transmit Buffer register, TXREG. TXIF

becomes valid in the second instruction cycle following

the load instruction. Polling TXIF immediately following a

load of TXREG will return invalid results.

While flag bit, TXIF, indicates the status of the TXREG

status of the TSR register. Status bit, TRMT, is a read-

only bit, which is set when the TSR register is empty.

No interrupt logic is tied to this bit, so the user has to

poll this bit in order to determine if the TSR register is

empty.

BRG Value

RX pin

ABDEN bit

RCIF bit

Bit 0

Bit 1

(Interrupt)

Read

RCREG

BRG Clock

Start

Auto-Cleared

Set by User

XXXXh

0000h

Edge #1

Bit 2

Bit 3

Edge #2

Bit 4

Bit 5

Edge #3

Bit 6

Bit 7

Edge #4

Edge #5

001Ch

Note 1:

The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.

SPBRG

XXXXh

1Ch

SPBRGH

XXXXh

00h

Stop Bit

Note 1: The TSR register is not mapped in data

memory, so it is not available to the user.

2: Flag bit, TXIF, is set when enable bit,

TXEN, is set.

PIC18F1220E/SOSQTP Datasheet(PDF) 142 Page - Microchip Technology

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