PIC18F1220ESLASHSOSQTP datasheet(173/308 Pages) MICROCHIP

173 / 308 page

DS39605F-page 171

PIC18F1220/1320

19.0

SPECIAL FEATURES OF

THE CPU

PIC18F1220/1320 devices include several features

intended to maximize system reliability, minimize cost

through elimination of external components and offer

code protection. These are:

• Oscillator Selection

• Resets:

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor

• Two-Speed Start-up

• Code Protection

• ID Locations

• In-Circuit Serial Programming

Several oscillator options are available to allow the part

to fit the application. The RC oscillator option saves

system cost, while the LP crystal option saves power.

These are discussed in detail in Section 2.0 “Oscillator

Configurations”.

A complete discussion of device Resets and interrupts

is available in previous sections of this data sheet.

In addition to their Power-up and Oscillator Start-up

Timers provided for Resets, PIC18F1220/1320 devices

have a Watchdog Timer, which is either permanently

enabled via

the

configuration bits, or

software

controlled (if configured as disabled).

The inclusion of an internal RC oscillator also provides

the additional benefits of a Fail-Safe Clock Monitor

(FSCM) and Two-Speed Start-up. FSCM provides for

background monitoring of the peripheral clock and

automatic switchover in the event of its failure. Two-

Speed Start-up enables code to be executed almost

immediately on start-up, while the primary clock source

completes its start-up delays.

All of these features are enabled and configured by

setting the appropriate configuration register bits.

19.1

Configuration Bits

The configuration bits can be programmed (read as

‘0’), or left unprogrammed (read as ‘1’), to select vari-

ous device configurations. These bits are mapped

starting at program memory location 300000h.

The user will note that address 300000h is beyond the

user program memory space. In fact, it belongs to the

configuration memory space (300000h-3FFFFFh),

which can only be accessed using table reads and

table writes.

Programming the configuration registers is done in a

manner similar to programming the Flash memory. The

EECON1 register WR bit starts a self-timed write to the

configuration register. In normal operation mode, a

TBLWT

instruction, with the TBLPTR pointing to the

configuration register, sets up the address and the data

for the configuration register write. Setting the WR bit

starts a long write to the configuration register. The con-

figuration registers are written a byte at a time. To write

or erase a configuration cell, a TBLWT instruction can

write a ‘1’ or a ‘0’ into the cell. For additional details on

Flash programming, refer to Section 6.5 “Writing to

Flash Program Memory”.

TABLE 19-1:

CONFIGURATION BITS AND DEVICE IDS

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default/

Unprogrammed

Value

300001h

CONFIG1H

IESO

FSCM

—

FOSC3

FOSC2

FOSC1

FOSC0

11-- 1111

300002h

CONFIG2L

—

BORV1

BORV0

BOR

PWRTEN

---- 1111

300003h

CONFIG2H

—

WDTPS3

WDTPS2

WDTPS1

WDTPS0

WDT

---1 1111

300005h

CONFIG3H

MCLRE

—

1--- ----

300006h

CONFIG4L

DEBUG

—

—LVP

—STVR

1--- -1-1

300008h

CONFIG5L

—

—CP1

CP0

---- --11

300009h

CONFIG5H

CPD

CPB

—

11-- ----

30000Ah

CONFIG6L

—

WRT1

WRT0

---- --11

30000Bh

CONFIG6H

WRTD

WRTB

WRTC

—

111- ----

30000Ch

CONFIG7L

—

EBTR1

EBTR0

---- --11

30000Dh

CONFIG7H

—EBTRB

—

-1-- ----

3FFFFEh

DEVID1(1)

DEV2

DEV1

DEV0

REV4

REV3

REV2

REV1

REV0

xxxx xxxx

(1)

3FFFFFh

DEVID2(1)

DEV10

DEV9

DEV8

DEV7

DEV6

DEV5

DEV4

DEV3

0000 0111

Legend:

= unknown, u = unchanged, – = unimplemented. Shaded cells are unimplemented, read as ‘0’.

Note

See Register 19-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.

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