PIC18F1220ESLASHSOSQTP datasheet(169/308 Pages) MICROCHIP

169 / 308 page

DS39605F-page 167

PIC18F1220/1320

18.1

Control Register

The Low-Voltage Detect Control register controls the

operation of the Low-Voltage Detect circuitry.

LVDCON REGISTER

U-0

R-0

R/W-0

R/W-1

R/W-0

R/W-1

—

IRVST

LVDEN

LVDL3

LVDL2

LVDL1

LVDL0

bit 7

bit 0

bit 7-6

Unimplemented: Read as ‘0’

bit 5

IRVST: Internal Reference Voltage Stable Flag bit

= Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified

voltage range

= Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the

specified voltage range and the LVD interrupt should not be enabled

bit 4

LVDEN: Low-Voltage Detect Power Enable bit

= Enables LVD, powers up LVD circuit

= Disables LVD, powers down LVD circuit

bit 3-0

LVDL3:LVDL0: Low-Voltage Detection Limit bits

1111

= External analog input is used (input comes from the LVDIN pin)

1110

= 4.04V-5.15V

1101

= 3.76V-4.79V

1100

= 3.58V-4.56V

1011

= 3.41V-4.34V

1010

= 3.23V-4.11V

1001

= 3.14V-4.00V

1000

= 2.96V-3.77V

0111

= 2.70V-3.43V

0110

= 2.53V-3.21V

0101

= 2.43V-3.10V

0100

= 2.25V-2.86V

0011

= 2.16V-2.75V

0010

= 1.99V-2.53V

0001

= Reserved

0000

= Reserved

Note:

LVDL3:LVDL0 modes, which result in a trip point below the valid operating voltage

of the device, are not tested.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

PIC18F1220E/SOSQTP Datasheet(PDF) 169 Page - Microchip Technology

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