PIC18F1220ESLASHSOSQTP datasheet(166/308 Pages) MICROCHIP

166 / 308 page

PIC18F1220/1320

DS39605F-page 164

17.8

Use of the CCP1 Trigger

An A/D conversion can be started by the “special event

trigger” of the CCP1 module. This requires that the

CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro-

grammed as ‘1011’ and that the A/D module is enabled

(ADON bit is set). When the trigger occurs, the

GO/DONE bit will be set, starting the A/D acquisition

and conversion and the Timer1 (or Timer3) counter will

be reset to zero. Timer1 (or Timer3) is reset to auto-

matically repeat the A/D acquisition period with minimal

software overhead (moving ADRESH/ADRESL to the

desired

location).

The

appropriate

analog

input

channel must be selected and the minimum acquisition

period is either timed by the user, or an appropriate

TACQ time selected before the “special event trigger”

sets the GO/DONE bit (starts a conversion).

If the A/D module is not enabled (ADON is cleared), the

“special event trigger” will be ignored by the A/D

module, but will still reset the Timer1 (or Timer3)

counter.

TABLE 17-2:

SUMMARY OF A/D REGISTERS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

INTCON

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 0000

PIR1

—ADIF

RCIF

TXIF

—

CCP1IF

TMR2IF

TMR1IF

-000 -000

PIE1

—ADIE

RCIE

TXIE

—

CCP1IE

TMR2IE

TMR1IE

-000 -000

IPR1

—ADIP

RCIP

TXIP

—

CCP1IP

TMR2IP

TMR1IP

-111 -111

PIR2

OSCFIF

—

EEIF

—

LVDIF

TMR3IF

—

0--0 -00-

PIE2

OSCFIE

—

EEIE

—

LVDIE

TMR3IE

—

0--0 -00-

IPR2

OSCFIP

—

EEIP

—

LVDIP

TMR3IP

—

1--1 -11-

ADRESH

A/D Result Register High Byte

xxxx xxxx

uuuu uuuu

ADRESL

A/D Result Register Low Byte

xxxx xxxx

uuuu uuuu

ADCON0

VCFG1

VCFG0

—

CHS2

CHS1

CHS0

GO/DONE

ADON

00-0 0000

ADCON1

—

PCFG6

PCFG5

PCFG4

PCFG3

PCFG2

PCFG1

PCFG0

-000 0000

ADCON2

ADFM

—

ACQT2

ACQT1

ACQT0

ADCS2

ADCS1

ADCS0

0-00 0000

PORTA

RA7(3)

RA6(2)

RA5(1)

RA4

RA3

RA2

RA1

RA0

qq0x 0000

uu0u 0000

TRISA

TRISA7(3) TRISA6(2)

—

PORTA Data Direction Register

qq-1 1111

11-1 1111

PORTB

Read PORTB pins, Write LATB Latch

xxxx xxxx

uuuu uuuu

TRISB

PORTB Data Direction Register

1111 1111

LATB

PORTB Output Data Latch

xxxx xxxx

uuuu uuuu

Legend:

= unknown, u = unchanged, q = depends on CONFIG1H<3:0>, – = unimplemented, read as ‘0’.

Shaded cells are not used for A/D conversion.

Note

RA5 port bit is available only as an input pin when the MCLRE bit in the configuration register is ‘0’.

RA6 and TRISA6 are available only when the primary oscillator mode selection offers RA6 as a port pin; otherwise, RA6

always reads ‘0’, TRISA6 always reads ‘1’ and writes to both are ignored (see CONFIG1H<3:0>).

RA7 and TRISA7 are available only when the internal RC oscillator is configured as the primary oscillator in

CONFIG1H<3:0>; otherwise, RA7 always reads ‘0’, TRISA7 always reads ‘1’ and writes to both are ignored.

PIC18F1220E/SOSQTP Datasheet(PDF) 166 Page - Microchip Technology

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