PIC18F1220ESLASHSOSQTP datasheet(162/308 Pages) MICROCHIP

162 / 308 page

PIC18F1220/1320

DS39605F-page 160

17.1

A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 17-2. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance varies over the device voltage

(VDD). The source impedance affects the offset voltage

at the analog input (due to pin leakage current). The

maximum recommended impedance for analog

sources is 2.5 k

Ω. After the analog input channel is

selected (changed), the channel must be sampled for

at least the minimum acquisition time before starting a

conversion.

calculate

the

minimum

acquisition

time,

Equation 17-1 may be used. This equation assumes

that 1/2 LSb error is used (1024 steps for the A/D). The

1/2 LSb error is the maximum error allowed for the A/D

to meet its specified resolution.

Example 17-1 shows the calculation of the minimum

required acquisition time, TACQ. This calculation is

based

the

following

application

system

assumptions:

CHOLD

120 pF

2.5 k

Conversion Error

≤

1/2 LSb

VDD

=5V

→ RSS = 7 kΩ

Temperature

°C (system max.)

VHOLD

0V @ time = 0

17.2

A/D VREF+ and VREF- References

If external voltage references are used instead of the

internal AVDD and AVSS sources, the source imped-

ance of the VREF+ and VREF- voltage sources must be

considered. During acquisition, currents supplied by

these sources are insignificant. However, during

conversion, the A/D module sinks and sources current

through the reference sources.

In order to maintain the A/D accuracy, the voltage

reference source impedances should be kept low to

reduce voltage changes. These voltage changes occur

as reference currents flow through the reference

source impedance. The maximum recommended

impedance of the VREF+ and VREF- external

reference voltage sources is 250

Ω.

EQUATION 17-1:

ACQUISITION TIME

EQUATION 17-2:

A/D MINIMUM CHARGING TIME

EXAMPLE 17-1:

CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

Note:

When the conversion is started, the

holding capacitor is disconnected from the

input pin.

TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient

=TAMP + TC + TCOFF

VHOLD =

(

ΔVREF – (ΔVREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))

-(CHOLD)(RIC + RSS + RS) ln(1/2048)

TACQ =TAMP + TC + TCOFF

TAMP =5

μs

TCOFF = (Temp – 25ºC)(0.05

μs/ºC)

(50ºC – 25ºC)(0.05

μs/ºC)

1.25

μs

Temperature coefficient is only required for temperatures > 25ºC. Below 25ºC, TCOFF = 0

μs.

=-(CHOLD)(RIC + RSS + RS) ln(1/2047)

μs

-(120 pF) (1 k

Ω + 7 kΩ + 2.5 kΩ) ln(0.0004883) μs

9.61

μs

TACQ =5

μs + 1.25 μs + 9.61 μs

12.86

μs

PIC18F1220E/SOSQTP Datasheet(PDF) 162 Page - Microchip Technology

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