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PIC18F1220E/SOSQTP Datasheet(PDF) 161 Page - Microchip Technology

Part # PIC18F1220E/SOSQTP
Description  18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers
PDF  308 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F1220E/SOSQTP Datasheet(HTML) 161 Page - Microchip Technology

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© 2007 Microchip Technology Inc.
DS39605F-page 159
PIC18F1220/1320
The value in the ADRESH/ADRESL registers is not
modified for a Power-on Reset. The ADRESH/ADRESL
registers will contain unknown data after a Power-on
Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 17.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
To do an A/D Conversion:
1.
Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
2.
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3.
Wait the required acquisition time (if required).
4.
Start conversion:
• Set GO/DONE bit (ADCON0 register)
5.
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6.
Read A/D Result registers (ADRESH:ADRESL);
clear bit, ADIF, if required.
7.
For the next conversion, go to step 1 or step 2,
as required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
FIGURE 17-2:
ANALOG INPUT MODEL
VAIN
CPIN
Rs
ANx
5 pF
VDD
VT = 0.6V
VT = 0.6V
ILEAKAGE
RIC
≤ 1k
Sampling
Switch
SS
RSS
CHOLD = 120 pF
VSS
6V
Sampling Switch
5V
4V
3V
2V
56 7 8 9 10 11
(k
Ω)
VDD
± 500 nA
Legend:
CPIN
= input capacitance
VT
= threshold voltage
ILEAKAGE = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
SS
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
RSS
= sampling switch resistance



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