PIC18F1220ESLASHSOSQTP datasheet(165/308 Pages) MICROCHIP

165 / 308 page

DS39605F-page 163

PIC18F1220/1320

17.7

A/D Conversions

Figure 17-3 shows the operation of the A/D converter

after the GO bit has been set and the ACQT2:ACQT0

bits are cleared. A conversion is started after the follow-

ing instruction to allow entry into Low-Power Sleep

mode before the conversion begins.

Figure 17-4 shows the operation of the A/D converter

after the GO bit has been set and the ACQT2:ACQT0

bits are set to ‘010’ and selecting a 4 TAD acquisition

time before the conversion starts.

Clearing the GO/DONE bit during a conversion will

abort the current conversion. The A/D Result register

pair will NOT be updated with the partially completed

A/D

conversion

sample.

This

means

the

ADRESH:ADRESL registers will continue to contain

the value of the last completed conversion (or the last

value written to the ADRESH:ADRESL registers).

After the A/D conversion is completed or aborted, a

2TAD wait is required before the next acquisition can

be started. After this wait, acquisition on the selected

channel is automatically started.

FIGURE 17-3:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

FIGURE 17-4:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

Note:

The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8

TAD11

Set GO bit

Holding capacitor is disconnected from analog input (typically 100 ns)

TAD9 TAD10

TCY – TAD

Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

Conversion Starts

Set GO bit

(Holding capacitor is disconnected)

Next Q4: ADRESH:ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is reconnected to analog input.

Conversion Starts

(Holding capacitor continues

acquiring input)

TACQT Cycles

TAD Cycles

Automatic

Acquisition

Time

PIC18F1220E/SOSQTP Datasheet(PDF) 165 Page - Microchip Technology

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