PIC16C72-04SLASHSP datasheet(48/124 Pages) MICROCHIP

48 / 124 page

PIC16C72 Series

DS39016A-page 48

Preliminary

8.4.1.1

ADDRESSING

Once the SSP module has been enabled, it waits for a

START condition to occur. Following the START condi-

tion, the 8-bits are shifted into the SSPSR register. All

incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match, and the BF

and SSPOV bits are clear, the following events occur:

The SSPSR register value is loaded into the

SSPBUF register.

The buffer full bit, BF is set.

An ACK pulse is generated.

SSP interrupt ﬂag bit, SSPIF (PIR1<3>) is set

(interrupt is generated if enabled) - on the falling

edge of the ninth SCL pulse.

In 10-bit address mode, two address bytes need to be

received by the slave. The ﬁve Most Signiﬁcant bits

(MSbs) of the ﬁrst address byte specify if this is a 10-bit

address. Bit R/W (SSPSTAT<2>) must specify a write

so the slave device will receive the second address

byte. For a 10-bit address the ﬁrst byte would equal

‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs

of the address. The sequence of events for 10-bit

address is as follows, with steps 7- 9 for slave-transmit-

ter:

Receive ﬁrst (high) byte of Address (bits SSPIF,

BF, and bit UA (SSPSTAT<1>) are set).

Update the SSPADD register with second (low)

byte of Address (clears bit UA and releases the

SCL line).

Read the SSPBUF register (clears bit BF) and

clear ﬂag bit SSPIF.

Receive second (low) byte of Address (bits

SSPIF, BF, and UA are set).

Update the SSPADD register with the ﬁrst (high)

byte of Address, if match releases SCL line, this

will clear bit UA.

Read the SSPBUF register (clears bit BF) and

clear ﬂag bit SSPIF.

Receive repeated START condition.

Receive ﬁrst (high) byte of Address (bits SSPIF

and BF are set).

Read the SSPBUF register (clears bit BF) and

clear ﬂag bit SSPIF.

TABLE 8-3

DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data

Transfer is Received

SSPSR

→ SSPBUF

Generate ACK

Pulse

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

SSPOV

Yes

PIC16C72-04/SP Datasheet(PDF) 48 Page - Microchip Technology

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