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PIC16C72-04/SP Datasheet(PDF) 72 Page - Microchip Technology

Part # PIC16C72-04/SP
Description  8-Bit CMOS Microcontrollers with A/D Converter
PDF  124 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16C72-04/SP Datasheet(HTML) 72 Page - Microchip Technology

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PIC16C72 Series
DS39016A-page 72
Preliminary
© 1998 Microchip Technology Inc.
FIGURE 10-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT
10.14
Program Verification/Code Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
10.15
ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are read-
able and writable during program/verify. It is recom-
mended that only the 4 least significant bits of the ID
location are used.
For ROM devices, these values are submitted along
with the ROM code.
10.16
In-Circuit Serial Programming™
PIC16CXXX family microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
For complete details of serial programming, please
refer to the In-Circuit Serial Programming (ICSP™)
Guide, DS30277.
Q1
Q2
Q3 Q4
Q1 Q2
Q3
Q4
Q1
Q1
Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1
Q2 Q3
Q4
Q1 Q2
Q3
Q4
OSC1
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC
PC+1
PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Latency
(Note 2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h)
Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2
0004h
0005h
Dummy cycle
TOST(2)
PC+2
Note
1:
XT, HS or LP oscillator mode assumed.
2:
TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3:
GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
4:
CLKOUT is not available in these osc modes, but shown here for timing reference.
Note:
Microchip does not recommend code pro-
tecting windowed devices.



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