PIC16C72-04SLASHSP datasheet(95/124 Pages) MICROCHIP

95 / 124 page

PIC16C72 Series

Preliminary

DS39016A-page 95

FIGURE 13-14: A/D CONVERSION TIMING

TABLE 13-13

A/D CONVERSION REQUIREMENTS

Param

No.

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

130

TAD

A/D clock period PIC16C72/LCR72

1.6

—

µs

TOSC based, VREF

≥ 2.5V

PIC16LC72/LCR72

2.0

—

µs

TOSC based, VREF full range

PIC16C72/LCR72

2.0

4.0

6.0

µs

A/D RC Mode

PIC16LC72/LCR72

2.5

6.0

9.0

µs

A/D RC Mode

131

TCNV

Conversion time

(not including S/H time) (Note 1)

—

9.5

—

TAD

132

TACQ

Acquisition time

Note 2

—

µs

The minimum time is the ampliﬁer

settling time. This may be used if

the "new" input voltage has not

changed by more than 1 LSb (i.e.,

20.0 mV @ 5.12V) from the last

sampled voltage (as stated on

CHOLD).

134

Tgo

Q4 to A/D clock start

—

TOSC/2 §

—

If the A/D clock source is selected

as RC, a time of TCY is added

before the A/D clock starts. This

allows the SLEEP instruction to be

executed.

135

Tswc

Switching from convert

→ sample time

1.5 §

—

TAD

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25

°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

This speciﬁcation ensured by design.

Note 1:

ADRES register may be read on the following TCY cycle.

Note 2:

See Section 9.1 for min conditions.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(TOSC/2) (1)

Note 1:

If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP

instruction to be executed.

1 TCY

134

PIC16C72-04/SP Datasheet(PDF) 95 Page - Microchip Technology

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