PIC16C72-04SLASHSP datasheet(63/124 Pages) MICROCHIP

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PIC16C72 Series

Preliminary

DS39016A-page 63

10.4

Power-On Reset (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (in the range of 1.5V - 2.1V). To

take advantage of the POR, just tie the MCLR pin

directly (or through a resistor) to VDD. This will eliminate

external RC components usually needed to create a

Power-on Reset. A maximum rise time for VDD is spec-

iﬁed. See Electrical Speciﬁcations for details. For a

slow rise time, see Figure 10-6.

When the device starts normal operation (exits the

reset condition), device operating parameters (voltage,

frequency, temperature,...) must be met to ensure oper-

ation. If these conditions are not met, the device must

be held in reset until the operating conditions are met.

Brown-out Reset may be used to meet the startup con-

ditions.

FIGURE 10-6: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW

VDD POWER-UP)

10.5

Power-up Timer (PWRT)

The Power-up Timer provides a ﬁxed 72 ms nominal

time-out on power-up only, from the POR. The Power-

up Timer operates on an internal RC oscillator. The

chip is kept in reset as long as the PWRT is active. The

PWRT’s time delay allows VDD to rise to an acceptable

level. A conﬁguration bit is provided to enable/disable

the PWRT.

The power-up time delay will vary from chip to chip due

to VDD, temperature, and process variation. See DC

parameters for details.

10.6

Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over. This ensures that the crystal oscil-

lator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

10.7

Brown-Out Reset (BOR)

A conﬁguration bit, BODEN, can disable (if clear/pro-

grammed) or enable (if set) the Brown-out Reset cir-

cuitry. If VDD falls below 4.0V (3.8V - 4.2V range) for

greater than parameter #35, the brown-out situation will

reset the chip. A reset may not occur if VDD falls below

4.0V for less than parameter #35. The chip will remain

in Brown-out Reset until VDD rises above BVDD. The

Power-up Timer will now be invoked and will keep the

chip in RESET an additional 72 ms. If VDD drops below

BVDD while the Power-up Timer is running, the chip will

go back into a Brown-out Reset and the Power-up

Timer will be initialized. Once VDD rises above BVDD,

the Power-up Timer will execute a 72 ms time delay.

The Power-up Timer should always be enabled when

Brown-out Reset is enabled.

Note 1: External Power-on Reset circuit is

required only if VDD power-up slope is too

slow. The diode D helps discharge the

capacitor quickly when VDD powers down.

2: R < 40 k

Ω is recommended to make sure

that voltage drop across R does not violate

the device’s electrical speciﬁcation.

3: R1 = 100

Ω to 1 kΩ will limit any current

ﬂowing into MCLR from external capacitor

C in the event of MCLR/VPP pin break-

down due to Electrostatic Discharge

(ESD) or Electrical Overstress (EOS).

VDD

MCLR

PIC16CXXX

PIC16C72-04/SP Datasheet(PDF) 63 Page - Microchip Technology

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