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PIC16C72-04/SP Datasheet(PDF) 61 Page - Microchip Technology |
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PIC16C72-04/SP Datasheet(HTML) 61 Page - Microchip Technology |
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61 / 124 page ![]() PIC16C72 Series © 1998 Microchip Technology Inc. Preliminary DS39016A-page 61 10.2.3 RC OSCILLATOR For timing insensitive applications the “RC” device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resis- tor (REXT) and capacitor (CEXT) values, and the operat- ing temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal pro- cess parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C compo- nents used. Figure 10-4 shows how the R/C combina- tion is connected to the PIC16CXXX family. FIGURE 10-4: RC OSCILLATOR MODE 10.3 Reset The PIC16CXXX family differentiates between various kinds of reset: • Power-on Reset (POR) • MCLR reset during normal operation • MCLR reset during SLEEP • WDT Reset (normal operation) • Brown-out Reset (BOR) Some registers are not affected in any reset condition; their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a “reset state” on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR reset during SLEEP, and Brown- out Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differ- ently in different reset situations as indicated in Table 10-4. These bits are used in software to deter- mine the nature of the reset. See Table 10-6 for a full description of reset states of all registers. A simplified block diagram of the on-chip reset circuit is shown in Figure 10-5. The PIC16C72/CR72 have a MCLR noise filter in the MCLR reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. OSC2/CLKOUT Cext Rext PIC16CXXX OSC1 Fosc/4 Internal clock VDD VSS Recommended values: 3 k Ω ≤ Rext ≤ 100 kΩ Cext > 20pF |
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