PIC16LC62B-04SLASHP datasheet(45/120 Pages) MICROCHIP

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PIC16C62B/72A

Preliminary

DS35008B-page 45

8.3.2

MASTER OPERATION

Master operation is supported in firmware using inter-

rupt generation on the detection of the START and

STOP conditions. The STOP (P) and START (S) bits

are cleared by a reset or when the SSP module is dis-

abled. The STOP (P) and START (S) bits will toggle

based on the START and STOP conditions. Control of

the I2C bus may be taken when the P bit is set, or the

bus is idle and both the S and P bits are clear.

In master operation, the SCL and SDA lines are manip-

ulated in software by clearing the corresponding

TRISC<4:3> bit(s). The output level is always low, irre-

spective of the value(s) in PORTC<4:3>. So when

transmitting data, a ’1’ data bit must have the

TRISC<4> bit set (input) and a ’0’ data bit must have

the TRISC<4> bit cleared (output). The same scenario

is true for the SCL line with the TRISC<3> bit.

The following events will cause SSP Interrupt Flag bit,

SSPIF, to be set (SSP Interrupt if enabled):

• START condition

• STOP condition

• Byte transfer completed

Master operation can be done with either the slave

mode idle (SSPM3:SSPM0 = 1011) or with the slave

active. When both master operation and slave modes

are used, the software needs to differentiate the

source(s) of the interrupt.

For more information on master operation, see

AN554

- Software Implementation of I2C Bus Master.

8.3.3

MULTI-MASTER OPERATION

In multi-master operation, the interrupt generation on

the detection of the START and STOP conditions

allows the determination of when the bus is free. The

STOP (P) and START (S) bits are cleared from a reset

or when the SSP module is disabled. The STOP (P)

and START (S) bits will toggle based on the START and

STOP conditions. Control of the I2C bus may be taken

when bit P (SSPSTAT<4>) is set, or the bus is idle and

both the S and P bits clear. When the bus is busy,

enabling the SSP Interrupt will generate the interrupt

when the STOP condition occurs.

In multi-master operation, the SDA line must be moni-

tored to see if the signal level is the expected output

level. This check only needs to be done when a high

level is output. If a high level is expected and a low level

is present, the device needs to release the SDA and

SCL lines (set TRISC<4:3>). There are two stages

where this arbitration can be lost, these are:

• Address Transfer

• Data Transfer

When the slave logic is enabled, the slave continues to

receive. If arbitration was lost during the address trans-

fer stage, communication to the device may be in

progress. If addressed, an ACK pulse will be gener-

ated. If arbitration was lost during the data transfer

stage, the device will need to re-transfer the data at a

later time.

For more information on master operation, see

AN578

- Use of the SSP Module in the of I2C Multi-Master

Environment.

TABLE 8-3

REGISTERS ASSOCIATED WITH I2C OPERATION

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

resets

0Bh, 8Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

0Ch

PIR1

—

ADIF

—

SSPIF

CCP1IF TMR2IF TMR1IF

-0-- 0000

8Ch

PIE1

—

ADIE

—

SSPIE CCP1IE TMR2IE TMR1IE

-0-- 0000

13h

SSPBUF

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx

uuuu uuuu

93h

SSPADD

Synchronous Serial Port (I2C mode) Address Register

0000 0000

14h

SSPCON

WCOL

SSPOV SSPEN

CKP

SSPM3 SSPM2 SSPM1 SSPM0

0000 0000

94h

SSPSTAT

SMP(1)

CKE(1)

D/A

R/W

0000 0000

87h

TRISC

PORTC Data Direction register

1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.

Shaded cells are not used by SSP module in SPI mode.

Note 1:

Maintain these bits clear in I2C mode.

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