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PIC16LC62B-04/P Datasheet(PDF) 19 Page - Microchip Technology |
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PIC16LC62B-04/P Datasheet(HTML) 19 Page - Microchip Technology |
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19 / 120 page ![]() PIC16C62B/72A © 1999 Microchip Technology Inc. Preliminary DS35008B-page 19 3.0 I/O PORTS Some I/O port pins are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicro™ Mid-Range Reference Manual, (DS33023). 3.1 PORTA and the TRISA Register PORTA is a 6-bit wide bi-directional port. The corre- sponding data direction register is TRISA. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output, (i.e., put the contents of the output latch on the selected pin). The PORTA register reads the state of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. There- fore, a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. Pin RA5 is multiplexed with the SSP to become the RA5/SS pin. On the PIC16C72A device, other PORTA pins are mul- tiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. FIGURE 3-1: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS FIGURE 3-2: BLOCK DIAGRAM OF RA4/T0CKI PIN Note: On a Power-on Reset, pins with analog functions are configured as analog inputs with digital input buffers disabled . A digital read of these pins will return ’0’. Data Bus Q D Q CK Q D Q CK QD EN P N WR Port WR TRIS Data Latch TRIS Latch RD TRIS RD PORT VSS VDD I/O pin(1) Note 1: I/O pins have protection diodes to VDD and VSS. Analog input mode TTL input buffer To A/D Converter (72A only) (72A only) Data Bus WR PORT WR TRIS RD PORT Data Latch TRIS Latch RD TRIS Schmitt Trigger input buffer N VSS I/O pin(1) TMR0 clock input Q D Q CK Q D Q CK EN QD EN Note 1: I/O pin has protection diodes to VSS only. |
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