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PIC16LC62B-04/P Datasheet(PDF) 52 Page - Microchip Technology |
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PIC16LC62B-04/P Datasheet(HTML) 52 Page - Microchip Technology |
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52 / 120 page ![]() PIC16C62B/72A DS35008B-page 52 Preliminary © 1999 Microchip Technology Inc. 9.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 9-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the ana- log input (due to pin leakage current). The maximum recommended impedance for analog sources is 10 k Ω. After the analog input channel is selected (changed), this acquisition must pass before the con- version can be started. To calculate the minimum acquisition time, TACQ, see Equation 9-1. This equation calculates the acquisition time to within 1/2 LSb error (512 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified accuracy. In general; Assuming RS = 10k Ω Vdd = 3.0V (RSS = 10k Ω) Temp. = 50 °C (122°F) TACQ ≈ 13.0 µSec By increasing VDD and reducing RS and Temp., TACQ can be substantially reduced. FIGURE 9-2: ANALOG INPUT MODEL EQUATION 9-1: ACQUISITION TIME Note: When the conversion is started, the hold- ing capacitor is disconnected from the input pin. TACQ = = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient TAMP + TC + TCOFF TAMP = 5 µS TC = - (51.2pF)(1k Ω + RSS + RS) In(1/511) TCOFF = (Temp -25 °C)(0.05µS/°C) CPIN VA Rs ANx 5 pF VDD VT = 0.6V VT = 0.6V I leakage RIC ≤ 1k Sampling Switch SS RSS CHOLD = DAC capacitance VSS 6V RSS 5V 4V 3V 2V 5 678 9 10 11 (k Ω) VDD = 51.2 pF ± 500 nA Legend CPIN VT I leakage RIC SS CHOLD = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from DAC) various junctions |
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