PIC16LC62B-04SLASHP datasheet(95/120 Pages) MICROCHIP

95 / 120 page

Preliminary

DS35008B-page 95

PIC16C62B/72A

FIGURE 13-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)

TABLE 13-7:

EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

Param.

No.

Symbol

Characteristic

Min

Typ† Max Units

Conditions

TssL2scH,

TssL2scL

↓ to SCK↓ or SCK↑ input

TCY

——

TscH

SCK input high time

(slave mode)

Continuous

1.25TCY + 30

—

71A

Single Byte

—

Note 1

TscL

SCK input low time

(slave mode)

Continuous

1.25TCY + 30

—

72A

Single Byte

—

Note 1

TdiV2scH,

TdiV2scL

Setup time of SDI data input to SCK edge

100

—

73A

TB2B

Last clock edge of Byte1 to the 1st clock

edge of Byte2

1.5TCY + 40

—

Note 1

TscH2diL,

TscL2diL

Hold time of SDI data input to SCK edge

100

—

TdoR

SDO data output rise time PIC16CXX

—10

PIC16LCXX

—20

TdoF

SDO data output fall time

—

TscR

SCK output rise time

(master mode)

PIC16CXX

—10

PIC16LCXX

—20

TscF

SCK output fall time (master mode)

—

TscH2doV,

TscL2doV

SDO data output valid

after SCK edge

PIC16CXX

——

PIC16LCXX

—

100

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: Specification 73A is only required if specifications 71A and 72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

75, 76

MSb

LSb

BIT6 - - - - - -1

MSb IN

LSb IN

BIT6 - - - -1

Note:

Refer to Figure 13-4 for load conditions.

PIC16LC62B-04/P Datasheet(PDF) 95 Page - Microchip Technology

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