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PIC16LC62B-04/P Datasheet(PDF) 64 Page - Microchip Technology |
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PIC16LC62B-04/P Datasheet(HTML) 64 Page - Microchip Technology |
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64 / 120 page ![]() PIC16C62B/72A DS35008B-page 64 Preliminary © 1999 Microchip Technology Inc. 10.12 Watchdog Timer (WDT) The Watchdog Timer is a free running on-chip RC oscil- lator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. The WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watch- dog Timer Wake-up). The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. The WDT can be permanently disabled by clearing configuration bit WDTE (Section 10.1). The WDT time-out period (TWDT, parameter #31) is multiplied by the prescaler ratio, when the prescaler is assigned to the WDT. The prescaler assignment (assigned to either the WDT or Timer0) and prescaler ratio are set in the OPTION_REG register. . FIGURE 10-8: WATCHDOG TIMER BLOCK DIAGRAM FIGURE 10-9: SUMMARY OF WATCHDOG TIMER REGISTERS Note: The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition. Note: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed. Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2007h Config. bits BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: Shaded cells are not used by the Watchdog Timer. From TMR0 Clock Source (Figure 4-2) To TMR0 (Figure 4-2) Postscaler WDT Timer WDT Enable Bit 0 1 M U X PSA 8 - to - 1 MUX PS2:PS0 0 1 MUX PSA WDT Time-out Note: PSA and PS2:PS0 are bits in the OPTION_REG register. 8 |
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