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LIS2DS12 Datasheet(PDF) 33 Page - STMicroelectronics

Part # LIS2DS12
Description  ultra-low-power high-performance 3-axis "pico" accelerometer
PDF  68 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

LIS2DS12 Datasheet(HTML) 33 Page - STMicroelectronics

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LIS2DS12
Digital interfaces
68
6
Digital interfaces
The registers embedded inside the LIS2DS12 may be accessed through both the I2C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped to the same pins. To select/exploit the I2C interface, the
CS line must be tied high (i.e. connected to Vdd_IO).
6.1
I2C serial interface
The LIS2DS12 I2C is a bus slave. The I2C is employed to write data into registers whose
content can also be read back.
The relevant I2C terminology is given in the table below.
There are two signals associated with the I2C bus: the serial clock line (SCL) and the Serial
DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface. Both the lines must be connected to Vdd_IO through an external pull-
up resistor. When the bus is free, both the lines are high.
The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with
normal mode.
In order to disable the I2C block, CTRL2 (21h) (I2C_DISABLE) = 1 must be set.
Table 15. Serial interface pin description
Pin name
Pin description
CS
SPI enable
I2C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI
communication mode / I2C disabled)
SCL
SPC
I2C serial clock (SCL)
SPI serial port clock (SPC)
SDA
SDI
SDO
I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
SA0
SDO
I2C address selection (SA0)
SPI serial data output (SDO)
Table 16. I2C terminology
Term
Description
Transmitter
The device which sends data to the bus
Receiver
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a
transfer
Slave
The device addressed by the master



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