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LIS2DS12 Datasheet(PDF) 43 Page - STMicroelectronics |
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LIS2DS12 Datasheet(HTML) 43 Page - STMicroelectronics |
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43 / 68 page  DocID027753 Rev 4 43/68 LIS2DS12 Register description 68 Table 39. Control register 1 description ODR [3:0] is used to set the power mode and ODR selection. The following table lists the bit settings for power-down mode and each available frequency. Table 41. ODR register setting: high resolution (HR) and high frequencies (HF) The BDU bit is used to inhibit the update of the output registers until both upper and lower register parts are read. In default mode (BDU = ‘0’) the output register values are updated continuously. When the BDU is activated (BDU = ‘1’), the content of the output registers is not updated until both MSB and LSB are read which avoids reading values related to different sample times. ODR [3:0] Output data rate & power mode selection. Default value: 0000 (see Table 40) FS [1:0] Full-scale selection. Default value: 00 (00: ±2 g; 01: ±16 g; 10: ±4 g; 11: ±8 g) HF_ODR High-frequency ODR mode enable. Default value: 0 BDU Block data update. Default value: 0 (0: continuous update; 1: output registers not updated until MSB and LSB read) Table 40. ODR register setting: power down (PD) and low power (LP) ODR[3:0] HF_ODR ODR selection [Hz] Bit resolution Mode 0000 - - - PD 1000 - 1 10 LP 1001 - 12.5 10 LP 1010 - 25 10 LP 1011 - 50 10 LP 1100 - 100 10 LP 1101 - 200 10 LP 1110 - 400 10 LP 1111 - 800 10 LP ODR[3:0] HF_ODR ODR selection [Hz] Bit resolution Mode 0001 - 12.5 14 HR 0010 - 25 14 HR 0011 - 50 14 HR 0100 - 100 14 HR 0101 0 200 14 HR 0110 0 400 14 HR 0111 0 800 14 HR 0101 1 1600 12 HF 0110 1 3200 12 HF 0111 1 6400 12 HF |
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