TMP320C2811PBKA datasheet(105/147 Pages) TI

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6.19 SPI Master Mode Timing

Table 6−20. SPI Master Mode External Timing (Clock Phase = 0)†‡

NO.

SPI WHEN (SPIBRR + 1) IS EVEN

OR SPIBRR = 0 OR 2

SPI WHEN (SPIBRR + 1)

IS ODD AND SPIBRR > 3

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

tc(SPC)M

Cycle time, SPICLK

4tc(LCO)

128tc(LCO)

5tc(LCO)

127tc(LCO)

2§

tw(SPCH)M

Pulse duration, SPICLK high

(clock polarity = 0)

0.5tc(SPC)M−10

0.5tc(SPC)M

0.5tc(SPC)M−0.5tc(LCO)−10

0.5tc(SPC)M −0.5tc(LCO)

2§

tw(SPCL)M

Pulse duration, SPICLK low

(clock polarity = 1)

0.5tc(SPC)M−10

0.5tc(SPC)M

0.5tc(SPC)M−0.5tc(LCO)−10

0.5tc(SPC)M −0.5tc(LCO)

3§

tw(SPCL)M

Pulse duration, SPICLK low

(clock polarity = 0)

0.5tc(SPC)M−10

0.5tc(SPC)M

0.5tc(SPC)M+0.5tc(LCO)−10

0.5tc(SPC)M + 0.5tc(LCO)

3§

tw(SPCH)M

Pulse duration, SPICLK high

(clock polarity = 1)

0.5tc(SPC)M−10

0.5tc(SPC)M

0.5tc(SPC)M+0.5tc(LCO)−10

0.5tc(SPC)M + 0.5tc(LCO)

4§

td(SPCH-SIMO)M

Delay time, SPICLK high to

SPISIMO valid (clock polarity = 0)

− 10

4§

td(SPCL-SIMO)M

Delay time, SPICLK low to

SPISIMO valid (clock polarity = 1)

− 10

5§

tv(SPCL-SIMO)M

Valid time, SPISIMO data valid

after SPICLK low

(clock polarity = 0)

0.5tc(SPC)M−10

0.5tc(SPC)M+0.5tc(LCO)−10

5§

tv(SPCH-SIMO)M

Valid time, SPISIMO data valid

after SPICLK high

(clock polarity = 1)

0.5tc(SPC)M−10

0.5tc(SPC)M+0.5tc(LCO)−10

8§

tsu(SOMI-SPCL)M

Setup time, SPISOMI before

SPICLK low (clock polarity = 0)

8§

tsu(SOMI-SPCH)M

Setup time, SPISOMI before

SPICLK high (clock polarity = 1)

9§

tv(SPCL-SOMI)M

Valid time, SPISOMI data valid

after SPICLK low

(clock polarity = 0)

0.25tc(SPC)M−10

0.5tc(SPC)M −0.5tc(LCO)−10

9§

tv(SPCH-SOMI)M

Valid time, SPISOMI data valid

after SPICLK high

(clock polarity = 1)

0.25tc(SPC)M−10

0.5tc(SPC)M −0.5tc(LCO)−10

† The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.

‡ tc(SPC) = SPI clock cycle time = LSPCLK

LSPCLK

(SPIBRR ) 1)

tc(LCO) = LSPCLK cycle time

§ The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is not greater than the I/O buffer speed limit (20 MHz).

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TMP320C2811PBKA Datasheet(PDF) 105 Page - Texas Instruments

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