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TMP320C2811PBKA Datasheet(PDF) 109 Page - Texas Instruments

Part # TMP320C2811PBKA
Description  TMS320R2811, TMS320R2812 Digital Signal Processors
PDF  147 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMP320C2811PBKA Datasheet(HTML) 109 Page - Texas Instruments

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Electrical Specifications
109
June 2004
SPRS257
6.20 SPI Slave Mode Timing
Table 6−22. SPI Slave Mode External Timing (Clock Phase = 0)†‡
NO.
MIN
MAX
UNIT
12
tc(SPC)S
Cycle time, SPICLK
4tc(LCO)‡
ns
13§
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S−10
0.5tc(SPC)S
ns
13§
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)S−10
0.5tc(SPC)S
ns
14§
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)S−10
0.5tc(SPC)S
ns
14§
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S−10
0.5tc(SPC)S
ns
15§
td(SPCH-SOMI)S
Delay time, SPICLK high to SPISOMI valid
(clock polarity = 0)
0.375tc(SPC)S−10
ns
15§
td(SPCL-SOMI)S
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
0.375tc(SPC)S−10
ns
16§
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =0)
0.75tc(SPC)S
ns
16§
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =1)
0.75tc(SPC)S
ns
19§
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
0
ns
19§
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
0
ns
20§
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
0.5tc(SPC)S
ns
20§
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 1)
0.5tc(SPC)S
ns
† The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
‡ tc(SPC) = SPI clock cycle time = LSPCLK
4
or
LSPCLK
(SPIBRR ) 1)
tc(LCO) = LSPCLK cycle time
§ The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).



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