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TMP320C2811PBKA Datasheet(PDF) 108 Page - Texas Instruments |
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TMP320C2811PBKA Datasheet(HTML) 108 Page - Texas Instruments |
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108 / 147 page ![]() Electrical Specifications 108 June 2004 SPRS257 Data Valid 11 SPISOMI SPISIMO SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) Master In Data Must Be Valid Master Out Data Is Valid 1 7 6 10 3 2 SPISTE† † In the master mode, SPISTE goes active 0.5tc(SPC) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 6−22. SPI Master External Timing (Clock Phase = 1) |
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