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TMP320C2811PBKA Datasheet(PDF) 110 Page - Texas Instruments |
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TMP320C2811PBKA Datasheet(HTML) 110 Page - Texas Instruments |
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110 / 147 page ![]() Electrical Specifications 110 June 2004 SPRS257 20 15 SPISIMO SPISOMI SPICLK (clock polarity = 1) SPICLK (clock polarity = 0) SPISIMO Data Must Be Valid SPISOMI Data Is Valid 19 16 14 13 12 SPISTE† † In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 6−23. SPI Slave Mode External Timing (Clock Phase = 0) |
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