DP83848JSQSLASHNOPB datasheet(34/84 Pages) TI1

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MDC

MDIO

0 0

1 1

1 1 0 0 0 0 0 0 0

(STA)

Idle

Start

Opcode

(Read)

PHY Address

(PHYAD = 0Ch)

(00h = BMCR)

MDIO

(PHY)

0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 Z

Idle

DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

SNLS250E – MAY 2008 – REVISED APRIL 2015

www.ti.com

6.4.3.2

Serial Management Access Protocol

The serial control interface consists of two pins, Management Data Clock (MDC) and Management Data

Input/Output (MDIO). MDC has a maximum clock rate of 25 MHz and no minimum rate. The MDIO line is

bi-directional and may be shared by up to 32 devices. The MDIO frame format is shown below in Table 6-

The MDIO pin requires a pullup resistor (1.5 k

Ω) which, during IDLE and turnaround, will pull MDIO high.

In order to initialize the MDIO interface, the station management entity sends a sequence of 32 contiguous

logic ones on MDIO to provide the DP83848x with a sequence that can be used to establish

synchronization. This preamble may be generated either by driving MDIO high for 32 consecutive MDC

clock cycles, or by simply allowing the MDIO pullup resistor to pull the MDIO pin high during which time 32

MDC clock cycles are provided. In addition, 32 MDC clock cycles should be used to re-sync the device if

an invalid start, opcode, or turnaround bit is detected.

The DP83848x waits until it has received this preamble sequence before responding to any other

transaction. Once the DP83848x serial management port has been initialized no further preamble

sequencing is required until after a power on/reset, invalid Start, invalid Opcode, or invalid turnaround bit

has occurred.

The Start code is indicated by a <01> pattern. This assures the MDIO line transitions from the default idle

line state.

Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field.

To avoid contention during a read transaction, no device shall actively drive the MDIO signal during the

first bit of Turnaround. The addressed DP83848x drives the MDIO with a zero for the second bit of

turnaround and follows this with the required data. Figure 6-2 shows the timing relationship between MDC

and the MDIO as driven/received by the Station (STA) and the DP83848x (PHY) for a typical register read

access.

For write transactions, the station management entity writes data to the addressed DP83848x thus

eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity

by inserting <10>. Figure 6-3 shows the timing relationship for a typical MII register write access.

Table 6-4. Typical MDIO Frame Format

MII MANAGEMENT SERIAL PROTOCOL

Read Operation

Write Operation

Figure 6-2. Typical MDC/MDIO Read Operation

Detailed Description

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DP83848JSQ/NOPB Datasheet(PDF) 34 Page - Texas Instruments

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