DP83848JSQSLASHNOPB datasheet(12/84 Pages) TI1

12 / 84 page

DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

SNLS250E – MAY 2008 – REVISED APRIL 2015

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AC Timing Requirements (continued)

MIN

NOM

MAX

UNIT

100 Mb/s MII TRANSMIT TIMING (REFER TO Figure 5-4)

T2.4.1

TX_CLK High/Low Time

100 Mb/s Normal mode

T2.4.2

TXD[3:0], TX_EN Data Setup to TX_CLK

100 Mb/s Normal mode

T2.4.3

TXD[3:0], TX_EN Data Hold from TX_CLK

100 Mb/s Normal mode

100 Mb/s MII RECEIVE TIMING (REFER TO Figure 5-5)(3)

T2.5.1

RX_CLK High/Low Time

100 Mb/s Normal mode

T2.5.2

RX_CLK to RXD[3:0], RX_DV, RX_ER Delay

100 Mb/s Normal mode

100BASE-TX TRANSMIT PACKET LATENCY TIMING (REFER TO Figure 5-6)(4)

T2.6.1

TX_CLK to PMD Output Pair Latency

100 Mb/s Normal mode

bits

100BASE-TX TRANSMIT PACKET DEASSERTION TIMING (REFER TO Figure 5-7)(5)

T2.7.1

TX_CLK to PMD Output Pair Deassertion

100 Mb/s Normal mode

bits

100BASE-TX TRANSMIT TIMING (tR/F) AND JITTER) (REFER TO Figure 5-8)

(6) (7)

100 Mb/s PMD Output Pair tR and tF

T2.8.1

100 Mb/s tR and tF Mismatch

500

T2.8.2

100 Mb/s PMD Output Pair Transmit Jitter

1.4

100BASE-TX RECEIVE PACKET LATENCY TIMING (REFER TO Figure 5-9)(8)(9)(10)

T2.9.1

Carrier Sense ON Delay

100 Mb/s Normal mode

bits

T2.9.2

Receive Data Latency

100 Mb/s Normal mode

bits

100BASE-TX RECEIVE PACKET DEASSERTION TIMING (REFER TO Figure 5-10)(9)(11)

T2.10.1

Carrier Sense OFF Delay

100 Mb/s Normal mode

bits

10 Mb/s MII TRANSMIT TIMING (REFER TO Figure 5-11)(12)

T2.11.1

TX_CLK High/Low Time

10 Mb/s MII mode

190

200

210

T2.11.2

TXD[3:0], TX_EN Data Setup to TX_CLK fall

10 Mb/s MII mode

T2.11.3

TXD[3:0], TX_EN Data Hold from TX_CLK rise

10 Mb/s MII mode

10 Mb/s MII RECEIVE TIMING (REFER TOFigure 5-12)(13)

T2.12.1

RX_CLK High/Low Time

160

200

240

T2.12.2

RX_CLK to RXD[3:0], RX_DV Delay

10 Mb/s MII mode

100

RX_CLK rising edge delay from RXD[3:0], RX_DV

T2.12.3

10 Mb/s MII mode

100

Valid

10BASE-T TRANSMIT TIMING (START OF PACKET) (REFER TO Figure 5-13)(14)

Transmit Output Delay from the Falling Edge of

T2.13.1

10 Mb/s MII mode

3.5

bits

TX_CLK

10BASE-T TRANSMIT TIMING (END OF PACKET) (REFER TO Figure 5-14)

T2.14.1

End of Packet High Time (with 0 ending bit)

250

300

T2.14.2

End of Packet High Time (with 1 ending bit)

250

300

10BASE-T RECEIVE TIMING (START OF PACKET) (REFER TO Figure 5-15)(14)(15)

Carrier Sense Turnon Delay (PMD Input Pair to

T2.15.1

630

1000

CRS)

T2.15.2

RX_DV Latency

bits

(3)

RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high

and low times will not be violated.

(4)

For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of

TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.

(5)

Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the

first bit of the “T” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.

(6)

Normal Mismatch is the difference between the maximum and minimum of all rise and fall times.

(7)

Rise and fall times taken at 10% and 90% of the +1 or –1 amplitude.

(8)

Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.

(9)

1 bit time = 10 ns in 100 Mb/s mode.

(10) PMD Input Pair voltage amplitude is greater than the Signal Detect Turnon Threshold Value.

(11) Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.

(12) An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on

the falling edge of TX_CLK.

(13) RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low

times will not be violated.

(14) 1 bit time = 100 ns in 10 Mb/s mode.

(15) 10BASE-T RX_DV Latency is measured from first bit of preamble on the wire to the assertion of RX_DV

Specifications

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Product Folder Links: DP83848H DP83848J DP83848K DP83848M DP83848T

DP83848JSQ/NOPB Datasheet(PDF) 12 Page - Texas Instruments

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