DP83848JSQSLASHNOPB datasheet(35/84 Pages) TI1

35 / 84 page

MDC

MDIO

1 1

0 0

0 0 0 0 0

(STA)

Idle

Start

Opcode

(Write)

PHY Address

(PHYAD = 0Ch)

(00h = BMCR)

0 0 0

0 0 0 0 0 0 0 0 Z

Idle

0 0

DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

www.ti.com

SNLS250E – MAY 2008 – REVISED APRIL 2015

Figure 6-3. Typical MDC/MDIO Write Operation

6.4.3.3

Serial Management Preamble Suppression

The DP83848x supports a Preamble Suppression mode as indicated by a one in bit 6 of the Basic Mode

Status Register (BMSR, address 01h.) If the station management entity (that is, MAC or other

management controller) determines that all PHYs in the system support Preamble Suppression by

returning a one in this bit, then the station management entity need not generate preamble for each

management transaction.

The DP83848x requires a single initialization sequence of 32 bits of preamble following hardware/software

reset. This requirement is generally met by the mandatory pullup resistor on MDIO in conjunction with a

continuous MDC, or the management access made to determine whether Preamble Suppression is

supported.

While the DP83848x requires an initial preamble sequence of 32 bits for management initialization, it does

not require a full 32-bit sequence between each subsequent transaction. A minimum of one idle bit

between management transactions is required as specified in the IEEE 802.3 specification.

6.4.4

PHY Address

The 5 PHY address inputs pins are shared with the RXD[3:0] pins and COL pin as shown in Table 6-5.

Table 6-5. PHY Address Mapping

PIN #

PHYAD FUNCTION

RXD FUNCTION

PHYAD0

COL

PHYAD1

RXD_0

PHYAD2

RXD_1

PHYAD3

RXD_2

PHYAD4

RXD_3

The DP83848x can be set to respond to any of 32 possible PHY addresses through strap pins. The

information is latched into the PHYCR register (address 19h, bits [4:0]) at device power up and hardware

reset. The PHY Address pins are shared with the RXD and COL pins. Each DP83848x or port sharing an

MDIO bus in a system must have a unique physical address.

The DP83848x supports PHY Address strapping values 0 (<00000>) through 31 (<11111>). Strapping

PHY Address 0 puts the part into Isolate Mode. It should also be noted that selecting PHY Address 0

through an MDIO write to PHYCR will not put the device in Isolate Mode. See Section 6.4.4.1 for more

information.

For further detail relating to the latch-in timing requirements of the PHY Address pins, as well as the other

hardware configuration pins, refer to the Reset summary in Section 6.4.6.

Because the PHYAD[0] pin has weak internal pullup resistor and PHYAD[4:1] pins have weak internal

pulldown resistors, the default setting for the PHY address is 00001 (01h).

Refer to Figure 6-4 for an example of a PHYAD connection to external components. In this example, the

PHYAD strapping results in address 00011 (03h).

Detailed Description

Submit Documentation Feedback

Product Folder Links: DP83848H DP83848J DP83848K DP83848M DP83848T

DP83848JSQ/NOPB Datasheet(PDF) 35 Page - Texas Instruments

DP83848JSQ/NOPB Datasheet(HTML) 35 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Datasheet Download

Link URL