DP83848JSQSLASHNOPB datasheet(58/84 Pages) TI1

58 / 84 page

DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

SNLS250E – MAY 2008 – REVISED APRIL 2015

www.ti.com

Table 6-18. PHY Status Register (PHYSTS), address 0x10 (continued)

Bit

Bit Name

Default

Description

Duplex Status

0, RO

Duplex:

This bit indicates duplex status and is determined from Auto-Negotiation or Forced Modes.

1 = Full duplex mode.

0 = Half duplex mode.

Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid

link or if Auto-Negotiation is disabled and there is a valid link.

Speed Status

0, RO

Speed10:

This bit indicates the status of the speed and is determined from Auto-Negotiation or Forced

Modes.

1 = 10 Mb/s mode.

0 = 100 Mb/s mode.

Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid

link or if Auto-Negotiation is disabled and there is a valid link.

Link Status

0, RO

Link Status:

This bit is a duplicate of the Link Status bit in the BMSR register, except that it will not be

cleared upon a read of the PHYSTS register.

1 = Valid link established (for either 10 or 100 Mb/s operation)

0 = Link not established.

6.6.1.2.2 False Carrier Sense Counter Register (FCSCR)

This counter provides information required to implement the “False Carriers” attribute within the MAU

managed object class of Clause 30 of the IEEE 802.3 specification.

Table 6-19. False Carrier Sense Counter Register (FCSCR), address 0x14

Bit

Bit Name

Default

Description

15:8

RESERVED

0, RO

RESERVED: Writes ignored, Read as 0

7:0

FCSCNT[7:0]

0, RO / COR

False Carrier Event Counter:

This 8-bit counter increments on every false carrier event. This counter sticks when it

reaches its max count (FFh).

6.6.1.2.3 Receiver Error Counter Register (RECR)

This counter provides information required to implement the “Symbol Error During Carrier” attribute within

the PHY managed object class of Clause 30 of the IEEE 802.3 specification.

Table 6-20. Receiver Error Counter Register (RECR), address 0x15

Bit

Bit Name

Default

Description

15:8

RESERVED

0, RO

RESERVED: Writes ignored, Read as 0

7:0

RXERCNT[7:0]

0, RO / COR

RX_ER Counter:

When a valid carrier is present and there is at least one occurrence of an invalid data

symbol, this 8-bit counter increments for each receive error detected. This event can

increment only once per valid carrier event. If a collision is present, the attribute will not

increment. The counter sticks when it reaches its max count.

Detailed Description

Submit Documentation Feedback

Product Folder Links: DP83848H DP83848J DP83848K DP83848M DP83848T

DP83848JSQ/NOPB Datasheet(PDF) 58 Page - Texas Instruments

DP83848JSQ/NOPB Datasheet(HTML) 58 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Datasheet Download

Link URL