DP83848JSQSLASHNOPB datasheet(37/84 Pages) TI1

37 / 84 page

DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

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SNLS250E – MAY 2008 – REVISED APRIL 2015

It is important to understand that while Auto-Negotiation with the use of Fast Link Pulse code words can

interpret and configure to full-duplex operation, parallel detection can not recognize the difference between

full and half-duplex from a fixed 10 Mb/s or 100 Mb/s link partner over twisted pair. As specified in the

802.3 specification, if a far-end link partner is configured to a forced full duplex 100BASE-TX ability, the

parallel detection state machine in the partner would be unable to detect the full duplex capability of the

far-end link partner. This link segment would negotiate to a half duplex 100BASE-TX configuration (same

scenario for 10 Mb/s).

6.4.6

Reset Operation

The DP83848x includes an internal power-on reset (POR) function and does not need to be explicitly reset

for normal operation after power up. If required during normal operation, the device can be reset by a

hardware or software reset.

6.4.6.1

Hardware Reset

A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1 µs, to

the RESET_N. This will reset the device such that all registers will be reinitialized to default values and the

hardware configuration values will be re-latched into the device (similar to the power-up/reset operation).

6.4.6.2

Software Reset

A software reset is accomplished by setting the reset bit (bit 15) of the Basic Mode Control Register

(BMCR). The period from the point in time when the reset bit is set to the point in time when software

reset has concluded is approximately 1 µs.

The software reset will reset the device such that all registers will be reinitialized to default values and the

hardware configuration values will be re-latched into the device. Software driver code must wait 3

μs

following a software reset before allowing further serial MII operations.

6.4.7

Power Down

The device can be put in a Power Down mode by setting bit 11 (Power Down) in the Basic Mode Control

6.5

Programming

6.5.1

Architecture

This section describes the operations within each transceiver module, 100BASE-TX and 10BASE-T. Each

operation consists of several functional blocks and described in the following:

•

100BASE-TX Transmitter

•

100BASE-TX Receiver

•

10BASE-T Transceiver Module

6.5.1.1

100BASE-TX Transmitter

The 100BASE-TX transmitter consists of several functional blocks which convert synchronous 4-bit nibble

data, as provided by the MII, to a scrambled MLT-3 125 Mb/s serial data stream. Because the 100BASE-

TX TP-PMD is integrated, the differential output pins, PMD Output Pair, can be directly routed to the

magnetics.

The Transmitter section consists of the following functional blocks:

•

Code-group Encoder and Injection block

•

Scrambler block (bypass option)

•

NRZ to NRZI encoder block

•

Binary to MLT-3 converter / Common Driver

Detailed Description

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DP83848JSQ/NOPB Datasheet(PDF) 37 Page - Texas Instruments

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