DP83848JSQSLASHNOPB datasheet(60/84 Pages) TI1

60 / 84 page

DP83848H, DP83848J, DP83848K, DP83848M, DP83848T

SNLS250E – MAY 2008 – REVISED APRIL 2015

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6.6.1.2.5 RMII and Bypass Register (RBR)

This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is

bypassed.

Table 6-22. RMII and Bypass Register (RBR), address 0x17

Bit

Bit Name

Default

Description

15:6

RESERVED

0, RO

RESERVED: Writes ignored, Read as 0.

RMII_MODE

Strap, RW

Reduced MII Mode:

0 = Standard MII Mode

1 = Reduced MII Mode

RMII_REV1_0

0, RW

Reduce MII Revision 1.0:

0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate deassertion of

CRS.

1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred. CRS_DV

will not toggle at the end of a packet.

RX_OVF_STS

0, RO

RX FIFO Over Flow Status:

0 = Normal

1 = Overflow detected

RX_UNF_STS

0, RO

RX FIFO Under Flow Status:

0 = Normal

1 = Underflow detected

1:0

ELAST_BUF[1:0]

1, RW

Receive Elasticity Buffer. This field controls the Receive Elasticity Buffer which allows for

frequency variation tolerance between the 50-MHz RMII clock and the recovered data. The

following value indicate the tolerance in bits for a single packet. The minimum setting allows

for standard Ethernet frame sizes at ±50 ppm accuracy for both RMII and Receive clocks. For

greater frequency tolerance the packet lengths may be scaled (that is, for ±100 ppm, the

packet lengths need to be divided by 2).

00 = 14 bit tolerance (up to 16800 byte packets)

01 = 2 bit tolerance (up to 2400 byte packets)

10 = 6 bit tolerance (up to 7200 byte packets)

11 = 10 bit tolerance (up to 12000 byte packets)

6.6.1.2.6 LED Direct Control Register (LEDCR)

This register provides the ability to directly control the LED outputs. It does not provide read access to the

LEDs.

Table 6-23. LED Direct Control Register (LEDCR), address 0x18

Bit

Bit Name

Default

Description

15:6

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

5(1)

DRV_SPDLED

0, RW

1 = Drive value of SPDLED bit onto LED_SPEED output

0 = Normal operation

DRV_LNKLED

0, RW

1 = Drive value of LNKLED bit onto LED_LINK output

0 = Normal operation

RESERVED

RESERVED: Must be zero.

2(1)

SPDLED

0, RW

Value to force on LED_SPEED output

LNKLED

0, RW

Value to force on LED_LINK output

RESERVED

RESERVED: Must be zero.

(1)

DP83848J/K only.

Detailed Description

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