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DP83848JSQ/NOPB Datasheet(PDF) 54 Page - Texas Instruments

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Part # DP83848JSQ/NOPB
Description  MII Serial Management Interface
PDF  84 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DP83848JSQ/NOPB Datasheet(HTML) 54 Page - Texas Instruments

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DP83848H, DP83848J, DP83848K, DP83848M, DP83848T
SNLS250E – MAY 2008 – REVISED APRIL 2015
www.ti.com
Table 6-13. Auto-Negotiation Advertisement Register (ANAR), address 0x04 (continued)
Bit
Bit Name
Default
Description
10
PAUSE
0, RW
PAUSE Support for Full Duplex Links:
The PAUSE bit indicates that the device is capable of providing the symmetric PAUSE
functions as defined in Annex 31B.
Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and
28B-3, respectively. Pause resolution status is reported in PHYCR[13:12].
1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer
and the pause function as specified in clause 31 and annex 31B of 802.3.
0= No MAC based full duplex flow control.
9
T4
0, RO/P
100BASE-T4 Support:
1= 100BASE-T4 is supported by the local device.
0 = 100BASE-T4 not supported.
8
TX_FD
Strap, RW
100BASE-TX Full Duplex Support:
1 = 100BASE-TX Full Duplex is supported by the local device.
0 = 100BASE-TX Full Duplex not supported.
7
TX
Strap, RW
100BASE-TX Support:
1 = 100BASE-TX is supported by the local device.
0 = 100BASE-TX not supported.
6
10_FD
RW
10BASE-T Full Duplex Support:
1 = 10BASE-T Full Duplex is supported by the local device.
0 = 10BASE-T Full Duplex not supported.
5
10
RW
10BASE-T Support:
1 = 10BASE-T is supported by the local device.
0 = 10BASE-T not supported.
4:0
Selector
<00001>, RW
Protocol Selection Bits:
These bits contain the binary encoded protocol selector supported by this port. <00001>
indicates that this device supports IEEE 802.3.
6.6.1.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The
content changes after the successful auto-negotiation if Next-pages are supported.
Table 6-14. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05
Bit
Bit Name
Default
Description
15
NP
0, RO
Next Page Indication:
0 = Link Partner does not desire Next Page Transfer.
1 = Link Partner desires Next Page Transfer.
14
ACK
0, RO
Acknowledge:
1 = Link Partner acknowledges reception of the ability data word.
0 = Not acknowledged.
The Auto-Negotiation state machine will automatically control the this bit based on the incoming
FLP bursts.
13
RF
0, RO
Remote Fault:
1 = Remote Fault indicated by Link Partner.
0 = No Remote Fault indicated by Link Partner.
12
RESERVED
0, RO
RESERVED for Future IEEE use:
Write as 0, read as 0.
11
ASM_DIR
0, RO
ASYMMETRIC PAUSE:
1 = Asymmetric pause is supported by the Link Partner.
0 = Asymmetric pause is not supported by the Link Partner.
10
PAUSE
0, RO
PAUSE:
1 = Pause function is supported by the Link Partner.
0 = Pause function is not supported by the Link Partner.
9
T4
0, RO
100BASE-T4 Support:
1 = 100BASE-T4 is supported by the Link Partner.
0 = 100BASE-T4 not supported by the Link Partner.
54
Detailed Description
Copyright © 2008–2015, Texas Instruments Incorporated
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Product Folder Links: DP83848H DP83848J DP83848K DP83848M DP83848T



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