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CP3SP33SMS/NOPB Datasheet(PDF) 146 Page - Texas Instruments |
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CP3SP33SMS/NOPB Datasheet(HTML) 146 Page - Texas Instruments |
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146 / 407 page  DS535 Endpoint Control Packet Encode/Decode RAM Controller CPU Interface Interrupts EP0 Control - Host USB Transceiver USB RAM Combine Endpoints EP0 Control - Function EP1-3 Control Transmit Packet Encode Rx Buff Tx Buff Rx Buff Tx Buff Packet Decode Cycle Control CRC Gen/Check UTM Synchronization Data Sync AHB Bus HS Negotiation Timers HNP/SRP Receive Host Transaction Scheduler Interrupt Control EP Reg. Decoder Common Regs Cycle Control FIFO Decoder CP3SP33 SNOSCW5 – MAY 2013 www.ti.com Each endpoint pipe has its own FIFO buffer. Table 21-1 shows the size of each FIFO, which is the maximum packet size which can be used with the corresponding endpoint pipe. In double-buffer mode, the maximum packet size is reduced by a factor of two. Table 21-1. Endpoint FIFO Buffer Size ENDPOINT DIRECTION FIFO SIZE (bytes) TRANSFER TYPE 0 Bidirectional 64 Control 1 Transmit 256 Isochronous 1 Receive 256 Isochronous 2 Transmit 64 Bulk/Interrupt 2 Receive 64 Bulk/Interrupt 3 Transmit 64 Bulk/Interrupt 3 Receive 64 Bulk/Interrupt The USB controller provides all encoding, decoding, and checking needed for sending and receiving USB packets. It interrupts the CPU only when endpoint data has been successfully transferred. When acting as the host for point-to-point communications, the USB controller maintains a frame counter and automatically schedules SOF, Isochronous, Interrupt, and Bulk transfers. It also includes support for the SRP and HRP protocols for point-to-point communications, defined in the USB On-The-Go specification. Figure 21-1. USB Controller Block Diagram 21.1 Modes of Operation The USB controller has two main modes of operation: 146 USB Controller Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :CP3SP33 |
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