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CP3SP33SMS/NOPB Datasheet(PDF) 70 Page - Texas Instruments |
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CP3SP33SMS/NOPB Datasheet(HTML) 70 Page - Texas Instruments |
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70 / 407 page  CP3SP33 SNOSCW5 – MAY 2013 www.ti.com Table 13-1. Maskable Interrupts Assignment (continued) IRQn DESCRIPTION ASC CHANNEL IRQ20 VTU1C (VTU Interrupt Request 3) IRQ19 VTU1D (VTU Interrupt Request 4) IRQ18 CAN1 IRQ17 UART1 Rx IRQ16 UART1 Tx IRQ15 UART2 Rx IRQ14 UART2 Tx IRQ13 UART3 Rx 3 IRQ12 UART3 Tx 2 IRQ11 ACCESS.bus 1 1 IRQ10 Microwire/SPI 1 Rx/Tx 0 IRQ9 ADC (Done) IRQ8 MIWU Interrupt 0 IRQ7 MIWU Interrupt 1 IRQ6 MIWU Interrupt 2 IRQ5 MIWU Interrupt 3 IRQ4 MIWU Interrupt 4 IRQ3 MIWU Interrupt 5 IRQ2 MIWU Interrupt 6 IRQ1 MIWU Interrupt 7 IRQ0 Reserved All reserved interrupt vectors must point to default or error interrupt handlers. 13.3 Interrupt Priority Groups When more than one interrupt is asserted, two levels of priority are used to determine which interrupt is taken: • Group Priority—each interrupt belongs to one of four priority groups numbered from 0 to 3, in which lower group numbers have higher priority. • Channel Priority—each channel has a unique channel number, in which higher channel numbers have higher priority. Group priority always takes precedence over channel priority. Channel priority is only used to resolve priority among interrupts in the same group. Any interrupt may belong to any group, as programmed in the INTGPAR and INTGPBR registers. The corresponding bits in each register assign the interrupt channel to one of the groups, as shown in Table 13-2. Table 13-2. Interrupt Priority Group Assignment Priority Group for IRQn INTGPBRn INTGPARn Group 0 (highest priority) 0 0 Group 1 0 1 Group 2 1 0 Group3 (lowest priority) 1 1 70 Interrupts Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :CP3SP33 |
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