CP3SP33SMSSLASHNOPB datasheet(93/407 Pages) TI1

93 / 407 page

Power Up

Power Down

Core VCC

DS516

IOVCC

Main

Clock

RESET

2.97V

1.62V

CP3SP33

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SNOSCW5 – MAY 2013

2. The RESET pin must then be held low until the Main Clock is stopped. The Main Clock will decay with

the same profile as IOVCC.

Meeting the power-down reset conditions ensures that software will not be executed at voltage levels that

may cause incorrect program execution or corruption of the flash memories. This situation must be

avoided because the Main Clock decays with the IOVCC supply rather than stopping immediately when

IOVCC falls below the minimum specified level.

The external reset circuits presented in the following sections provide varying levels of additional fault

tolerance and expandability and are presented as possible examples of solutions to be used with the

CP3SP33. It is important to note, however, that any design for the reset circuit and power supply must

meet the timing requirements shown in Figure 15-1.

Figure 15-1. Power-On Reset Timing

15.2.1 Simple External Reset

A simple external reset circuit with brown-out and glitch protection based on the LM809 3-Pin

Microprocessor Reset Circuit is shown in Figure 15-2. The LM809 produces a 240-ms logic low reset

pulse when the power supply rises above a threshold voltage. Various reset thresholds are available for

the LM809, however the options for 2.93V and 3.08V are most suitable for a CP3SP33 device operating

from an IO-VCC at 3.0V to 3.3V.

Reset

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CP3SP33SMS/NOPB Datasheet(PDF) 93 Page - Texas Instruments