CP3SP33SMSSLASHNOPB datasheet(12/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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Most modules operate from clocks derived from Main Clock or a PLL clock. Modules on the CPU core

AHB bus operate from HCLK Clock, while modules on the peripheral APB buses operate from PCLK

Clock. PCLK Clock is generated by dividing HCLK Clock by 1, 2, or 4. Some peripheral modules may use

one of several auxiliary clocks, which also are derived from Main Clock or a PLL clock using 12-bit

programmable prescalers.

In Power-Save mode, HCLK Clock is driven by Slow Clock, which is typically a 32.768 kHz signal

generated from an external clock network or a prescaled Main Clock may be used to eliminate the 32.768

kHz crystal network, for the most cost-sensitive applications. In the most power-sensitive applications,

operation from an external 32.768 kHz crystal network allows the high-frequency oscillator and PLLs to be

shut down.

In addition, the Clock and Reset module generates the device reset by using reset input signals coming

from an external reset, the watchdog timer, or the SDI debugging interface. A power-on reset (POR) circuit

eliminates the need for an external RC network. The POR circuit generates an internal reset of sufficient

length if the power supply rise time specification is met.

3.24 DMA Controller

The Direct Memory Access Controller (DMAC) can speed up data transfer between memory and I/O

devices or between two regions of memory, as compared to data transfers performed directly by the CPU.

Cycle stealing allows the CPU and the DMAC to interleave access to the CPU core bus for greater

utilization of the available bandwidth. The following on-chip modules can assert a DMA request to the

DMA controller:

•

USART 0 (2 request channels)

•

UART 1/2/3 (6 request channels

•

Advanced Audio Interface (6 request channels)

•

CVSD/PCM Converter 0/1 (8 request channels)

•

Microwire/SPI 0/1 (4 request channels)

•

ACCESS.bus 0/1 (2 request channels)

•

Codec (4 request channels)

•

I2S Interface (4 request channels)

The DSP has its own DMA controller which can be configured to accept DMA requests from peripherals

on the shared audio peripheral APB bus.

3.25 Serial Debug Interface

The Serial Debug Interface module (SDI module) provides a JTAG-based serial link to an external

debugger, for example running on a PC. In addition, the SDI module integrates an on-chip debug module,

which allows the user to set up to eight hardware breakpoints on instruction execution and data transfer.

The SDI module can act as a CPU bus master to access all memory-mapped resources, such as RAM

and peripherals. Therefore it also allows for fast program code download using the JTAG interface.

3.26 Development Support

In addition to providing the features needed for the next generation of embedded Bluetooth products, the

CP3SP33 devices are backed up by the software resources that designers need for rapid product

development, including an operating system, Bluetooth protocol stack implementation, peripheral drivers,

reference designs, and an integrated development environment. Combined with National’s LMX5252

Bluetooth radio transceiver, the CP3SP33 devices provide a total Bluetooth system solution.

Texas Instruments offers a complete and industry-proven application development environment for

CP3SP33 applications, including the IAR Embedded Workbench, iSYSTEM winIDEA and iC3000 Active

Emulator, Bluetooth Development Board, Bluetooth Protocol Stack, and Application Software. See your

Texas Instruments sales representative for current information on availability and features of emulation

equipment and evaluation boards.

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