CP3SP33SMSSLASHNOPB datasheet(54/407 Pages) TI1

54 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

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FREEZE

The Freeze bit controls whether the device is placed in Freeze mode, which is a debugging

mode that inhibits certain automatic state changes in register bits, such as timers and clear-

on-read registers. See Section 11.2 for more information about Freeze mode. The Serial

Debug Interface (SDI) also has the capability of putting the device in Freeze mode through

a separate mechanism.

0 – Freeze mode disabled.

1 – Freeze mode enabled.

11.5 Module Status Register (MSTAT)

The MSTAT register is a byte-wide, read-only register that indicates the general status of the device. The

MSTAT register format is shown below. At reset, the MSTAT register is initialized to 00h, except for bits 0

and 1 which are sampled from the ENV pins.

2M M1

ISPRST

WDRST

Reserved

OENV

The Operating Environment bits hold the states sampled from the ENV[1:0] input pins at reset.

These states are controlled by external hardware at reset and are held constant in the register

until the next reset.

WDRST

The Watchdog Reset bit indicates that a Watchdog timer reset has occurred. Write a 1 to this

bit to clear it. Power-on reset also clears this bit.

0 – No Watchdog timer reset has occurred since this bit was last cleared.

1 – A Watchdog timer reset has occurred since this bit was last cleared.

ISPRST

The Software ISP Reset bit indicates that a SWRESET(ISP) reset has occurred since the bit

was last cleared. This bit is cleared by a SWRESET(CLR) sequence or a power-on reset. See

the description of the SWRESET register for more information.

0 – No SWRESET(ISP) reset has occurred since this bit was last cleared.

1 – A SWRESET(ISP) reset has occurred since this bit was last cleared.

11.6 Software Reset Register (SWRESET)

The SWRESET register is an 8-bit, write-only register which provides a mechanism for software to initiate

a reset. There are two software reset sequences, called SWRESET(ISP) and SWRESET(CLR), which are

provided for compatibility with other CP3000 devices that have an in-system programming (ISP) mode,

however the CP3SP33 does not have an ISP mode.

To initiate a SWRESET(ISP) reset, write the value E1h to the SWRESET register, followed within 127

PCLK Clock cycles by writing the value 3Eh. The reset then follows immediately. After the

SWRESET(ISP) reset occurs, the ISPRST bit in the MSTAT register is set.

To initiate a SWRESET(CLR) reset, write the value E1h to the SWRESET register, followed within 127

PCLK Clock cycles by writing the value 0Eh. The reset then follows immediately. After the

SWRESET(CLR) reset occurs, the ISPRST bit in the MSTAT register is clear.

11.7 System Configuration Register (SYSCFG)

The SYSCFG register is a byte-wide, read/write register that indicates the general status of the device.

The SYSCFG register format is shown below. At reset, the SYSCFG register is initialized to 00h.

XDPUDIS

Reserved

USBIDDIGPUEN

USBHCLKDIS

BTHCKLDIS

RFCKEN

System Configuration

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